Design and implementation of GPS receiver based on ARM core

0 Introduction

As a mature navigation and positioning technology, the Global Positioning System (GPS) has become more and more widely used due to its remarkable features such as all-weather, high-precision, automation, and high efficiency, as well as its unique positioning navigation, timing and frequency, precision measurement and other powerful functions. The traditional GPS receiver designed with 8-bit single-chip microcomputer has great deficiencies in data processing, system performance improvement and function expansion. With the development of embedded technology, 32-bit microprocessors represented by ARM have been widely used in reality due to their advantages of high performance, low power consumption, low cost and small size.

This paper introduces a GPS receiver design that uses the ATR0600 and ATR0620 chips produced by Atmel. The ATR0600 chip is used as the RF front end of the receiver, and the ATR0620 chip with an embedded ARM7TDMI processor core is used as the digital baseband processor of the receiver. This solution has the characteristics of low power consumption, high performance, small size and low cost.

1 Basic components of GPS receiver

The main task of a GPS receiver is to track visible GPS satellites, obtain the measurement values ​​and navigation information required for positioning after data processing of the received satellite radio signals, and finally complete the positioning calculation and possible navigation tasks for the user. The internal structure of a GPS receiver is usually divided into three functional modules: radio frequency (RF) front-end processing, baseband digital signal processing (DSP), and positioning and navigation calculation, in the order of its workflow. Its basic composition is shown in Figure 1:

2 GPS receiver hardware design

The satellite signal is received by the antenna and directly enters the RF front end. The RF front end has a frequency conversion function, converting the RF signal into an intermediate frequency signal. After the intermediate frequency signal is sampled and quantized by the sampling signal, it is converted into a digital intermediate frequency signal. The digital intermediate frequency signal enters the baseband digital processor. After the baseband digital processor completes the processing of the satellite signal, it demodulates the navigation message, performs corresponding processing, and gives the required positioning information or provides specific application services.

2.1 Receiving Antenna

The receiving antenna is the first device for GPS receivers to process satellite signals. It converts the electromagnetic wave signals transmitted by GPS satellites into voltage or current signals for the receiver's RF front end to capture and process. Because the information that GPS receivers rely on for positioning basically all comes from the GPS satellite signals received by the antenna, the performance of the receiving antenna directly affects the positioning performance of the entire receiver, and its role and contribution to the receiver cannot be ignored.

The main technical requirements for the GPS receiver antenna are: receiving L1 signals with a frequency of 1575.42MHz; in order to match the polarization mode of the received GPS satellite signal and thus improve the receiving efficiency, the receiving antenna works in a right-hand circular polarization mode; the weak GPS satellite signal should be amplified as much as possible at the end close to the antenna to improve the noise performance of the entire receiving system, and the receiver uses an active antenna with a built-in low-noise amplifier (LAN); the impedance of the wire feeder is 50. In summary, this paper uses a vertical quad-helix antenna with high sensitivity, and the antenna is external when working.

2.2 RF front-end circuit design based on ATR0600

The radio frequency (RF) front-end module is located between the receiver antenna and the baseband digital signal processing module. It receives all visible GPS satellite signals through the antenna, and after filtering and amplification by the pre-filter and pre-amplifier, it is mixed with the sine wave local oscillator signal generated by the local oscillator and down-converted into an intermediate frequency (IF) signal. Finally, the intermediate frequency signal is discretized into a low-frequency digital intermediate frequency signal containing GPS signal components through the analog-to-digital (A/D) converter, and necessary filtering and gain control are performed in this process.
The RF front-end in this design is mainly composed of the ATR0600 chip produced by Atmel and the peripheral filtering circuit. It is a GPS receiver RF front-end IC chip with a single IF structure. The chip contains a mixer, IF amplifier, 2-bit analog-to-digital converter (ADC), crystal oscillator and other circuits. The chip has a very high degree of integration and very low power consumption (about 50w).

ATR0600 receives the 1575.42MHz L1 GPS signal through an external antenna. After the first level filtering and amplification by the low noise amplifier LNA, the signal is image-suppressed and isolated from the 1800MHz GSM band signal by the external SAW filter. The signal is mixed with the local oscillator signal with a reference frequency of 23.104 MHz, and the mixer down-converts the GPS signal to an intermediate frequency of 97.76MHz. After mixing, the signal passes through an LC bandpass filter and a variable gain amplifier (VGA), and is combined with an on-chip integrated intermediate frequency bandpass filter to filter the GSM interference signal. The VGA output drives the integrated 1.5bitA/D converter to convert the intermediate frequency signal into a 4.35MHz digital intermediate frequency signal. [page]

The internal structure of ATR0600 and its circuit application form are shown in Figure 2:

2.3 Baseband processor circuit based on ATR0620

The baseband digital signal processing module is the core part of the GPS receiver. It processes the digital intermediate frequency signal output by the RF front end to copy the local carrier and local pseudo code signal consistent with the received satellite signal, thereby capturing and tracking the GPS signal, and obtaining measurement values ​​such as GPS pseudorange and carrier phase, and demodulating the navigation message.

The baseband digital signal processing module is usually an organism that combines hardware and software, in which carrier demodulation and C/A code despreading are usually completed by a digital signal processor in the form of ASIC hardware, while the tracking loop control software running in the microprocessor adjusts the various operations of the digital signal processor through calculation. The ATR0620 chip produced by Atmel contains a 16-channel correlator based on the ARM7TDMI processing core. It has a high-performance 32-bit RISC structure and uses a 16-bit instruction system. It can use the ARM7TDMI microcontroller core and on-chip RAM to complete the GPS 16-channel correlator and peripheral device interface functions; using a large number of functional registers inside the chip can meet real-time control applications.

The external interface of ATR0620 and its signal connection with ATR0600 are shown in Figure 3.

2.4 GPS Receiver Circuit Design

The ATR0600 RF front end provides satellite signals, master clock signals and other control signals to the ATR0620, while the ATR0620 provides sampling signals to the ATR0600. Figure 4 is a block diagram of a GPS receiver designed using the ATR0600 and ATR0620 chips.

2.5 Storage module and communication interface

The CY7C1041 produced by Cypress is selected to expand the SRAM with a capacity of 4 Mb, which is selected by the chip select signal NSCS[I]. The FLASH is selected from the SST39VF400 chip with a capacity of 4 Mb produced by ST, which is selected by the chip select signal NSCS[0].

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Two communication interfaces are designed in the receiver: one is the JTAG debugging interface, which is connected to the JTAG emulator for development and debugging and downloading user programs; the other is the RS232 communication serial port, which is used to communicate with the host. The JTAG debugging circuit connection is shown in Figure 5.

3 GPS receiver software design

The user equipment of GPS is mainly composed of receiver hardware and processing software. Users receive GPS satellite signals through user equipment, obtain user position, speed and other information through signal processing, and finally achieve the purpose of navigation and positioning using GPS. The structure of GPS receiver software is shown in Figure 6. The program consists of two parts: assembly language program part (for booting and system initialization) and C language application program (for main navigation and positioning calculation). The software adopts parallel task structure as a whole, and the task switching is driven by the accumulated data IRQ interrupt signal generated by the correlator, and the pseudo code, carrier and data demodulation loop are updated in the interrupt service program.

The application software of GPS receiver varies according to different purposes, mainly including: data collection and analysis, satellite position calculation, time calculation, differential positioning and dynamic positioning, etc. The program on the GPS receiver of this design is mainly written in C language under the ARM-CLinux cross-compilation environment, and connected to the JAG emulator through the ARM7 JTAG interface for debugging and transplantation.

4 Conclusion

The GPS receiver designed in this paper adopts the GP4020 chip with embedded ARM7 core as the digital baseband processor of the receiver. Through experimental debugging, the bottleneck effect of the previous microprocessor is eliminated, and it has the characteristics of small size, low power consumption and high performance. Experimental PCB board size: 75 mmх50 mm xl2 mm; number of channels: 16; power consumption: less than 0.1 W; first positioning time: less than 41 s (cold start), less than 2.5s (hot start); positioning accuracy: 3 m.

References

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