Application of VHDL Language in FPGA/CPLD Development

1 Introduction
One of the key technologies of EDA (electronic design automation) is to use hardware description language (HDL) to describe circuit systems, including circuit structure, behavior, logic function and interface. For the development of FPGA and CPLD (field programmable gate array and complex programmable logic device, respectively), the more popular HDLs are VHDL, ABEL-HDL, AHDL, etc. Among them, VHDL has the strongest ability to describe the behavior of the system. It has been identified as a standard HDL by IEEE and is supported by all popular EDA software, thus becoming the best hardware description language in the field of system design. When designing circuit systems with VHDL, any complex circuit system can be regarded as a module corresponding to a design entity. In VHDL hierarchical design, the modules it designs can be either top-level entities or lower-level entities, but different description methods (such as behavior description or structure description) should be selected for modules at different levels. This article introduces in detail the method of developing FPGA/CPLD with VHDL language in the design example, as well as the advantages of using VHDL language compared with circuit diagram input and other HDL languages.
2 Design Examples
The design of a complex circuit system adopts a hierarchical design method that divides the system layer by layer according to function from top to bottom. In the top-level design, the connection relationship of each internal functional block and the external interface relationship should be described, while the actual logical function and specific implementation form of the functional block are described by the next layer module. In the bottom-level design of the system
, if VHDL is used for description, due to its strong ability to describe the behavior of the system, it is not necessary to refine the system layer by layer, thus avoiding the specific device structure, and directly describing and designing the module from the logical behavior. After that, the VHDL synthesizer in the EDA software will automatically synthesize the program into a netlist file of a specific target chip such as FPGA/CPLD, which will undoubtedly greatly simplify the design. The following is an example of the design of a digital clock.
The main functions of a digital clock are:
·It can count seconds, minutes, and hours (according to the 24-hour time system).
·The seconds, minutes, and hours can be adjusted.

According to the functional requirements of the digital clock, the digital clock can be divided into four functional blocks: second pulse generator, counter, time regulator and display circuit. These functional blocks can be further divided into smaller modules, such as the counter module can be further divided into second, minute and hour counters. The refinement process of other functional blocks will not be described in detail. The system block diagram of the digital clock is shown in Figure 1. In the figure, the P1 key is the four working state selection keys of automatic timing, time calibration, minute calibration and second calibration. The P2 key is the time calibration key for calibrating the hour, minute and second when the system is in the time calibration state. 32.768kHz is the crystal oscillator frequency as the pulse source. After the 14-level 2-frequency divider, the pulse signals of 1Hz, 2Hz and 1024Hz can be obtained at its highest, second highest and fifth output ends respectively. These three pulse signals are used as timing pulses, time calibration pulses and scanning clocks of the display circuit respectively. The following uses VHDL language to design the underlying hour counter. The hour counter is a 24-decimal BCD code counter, and its module schematic diagram is shown in Figure 2. Reset and clk are the asynchronous reset terminal and clock terminal respectively, and qb and qa are the four-digit BCD code output terminals for the tens and ones digits respectively. The implementation of the counting method of this module is relatively complicated. When the tens digit is 0 or 1, the ones digit is counted in decimal, and when the tens digit is 2, the ones digit is counted in 4-digit. If described by a circuit diagram, it is necessary to select and call several gates, triggers or macro units, and the called devices must be properly controlled. If the VHDL language is used to describe its functions, the problem becomes very simple.

The following is a 24-base BCD code counter count24 module designed in VHDL language:
ENTITY count24 IS


END count24—arc;
The part contained by the statements ENTITY and END count24 in the above program is called the entity of the program. Its circuit meaning is equivalent to the external interface of the device, and it is equivalent to a component symbol on the circuit diagram. This entity is a complete and independent language module, which describes the interface information of count24 and defines the input and output properties and data types of the port pins clk, reset, qa, and qb of count24; starting from the statement ARCHITECTURE and ending with END count24arc, it is a structure level. The structure level is used to describe the internal logical function of count24, which is equivalent to the internal circuit structure of the device in the circuit. The specific method of describing the logical function is to define two integer intermediate variables cntb and cnta in the process area of ​​the structure to represent the tens and ones respectively, and then use the IF statement to explain the counting and carry of these two variables when the clock arrives. When the process ends, the two intermediate variables are assigned to the output variables qb and qa respectively. The whole program is not long, and the logic description is very concise and clear.
After the above program is input, it must first be compiled by EDA software. This design uses the MAX+PLUS2II software of Altera Corporation in the United States. After the Compiler compiler in the software compiles, if there are any information, errors and warnings, they will be prompted in the VHDL compiler window, and the designer can modify the design according to the prompts. When the compilation is passed, the netlist building, logic synthesis, adaptation, division, time domain analysis, assembly, etc. have been automatically completed, and multiple files for subsequent work are generated. The success of the compilation indicates that a programming file has been established for the designed project, but it cannot guarantee that the design has a correct response in all possible situations. Therefore, after the compilation is passed, the Simulator simulator and Timing Analyzer tool of MAX+PLUSII must be used for functional simulation and timing simulation respectively to verify whether the design fully meets the requirements. If any problems are found, the original design must be returned for modification. No problems were found in the above modules after functional simulation and timing simulation. Figure 3 shows the simulation waveform of the above module. After the design of this module is completed, it is archived and called when the top-level file is established.
Next, use VHDL language to design all other modules in the bottom layer one by one, including: second and minute counters (both are 60-base counters), 14-level 2-frequency divider, 24-to-4 data selector, BCD seven-segment decoder, beat generator, etc. All programs are compiled and simulated by MAX+PLUS2II software. When the module design is completed, it must be archived and called when the top-level file is established.
In addition to the bottom-level modules, other modules at all levels (including the top level) are also suitable for description in VHDL language. It’s just that different description methods should be selected. When all modules in the bottom layer are designed, the structural description method in VHDL language is used to call the bottom-level modules and connect them with component call statements to establish the top-level file of the digital clock. The top-level file of the digital clock must also be compiled and simulated by EDA software. During this process, if necessary, you can open and view and modify the design of any level at any time. When it is finally confirmed that the design fully meets the design requirements, the compiled top-level file is downloaded to the target chip PFGA/CPLD.
In summary, the modules at all levels of the entire system are described in VHDL language, which has the following three advantages: (1) It can describe the behavior at the system level, describe and design the modules from the perspective of logical behavior, which greatly reduces the design difficulty. (2) The design ideas, circuit structures and logical relationships described are clear and easy to archive, view, maintain and modify. (3) It supports the decomposition of large-scale designs and the reuse of existing designs.
The above three advantages alone cannot be achieved by circuit diagram input and other HDL languages.

3 Conclusion
The larger the scale of integrated circuits, the more prominent the superiority of VHDL language. At present, FPGA/CPLD with millions of gates has entered practical use. VHDL's powerful system description ability, standardized programming structure and flexible statement expression style will surely enable it to undertake almost all design tasks of large system design.

1 Zhu Mingcheng, Sun Jin. VHDL Design Technology for Programmable Logic Systems. Nanjing: Southeast University Press, 1998
2 Hou Boheng, Gu Xin. VHDL Hardware Description Language and Digital Logic Circuit Design. Xi'an: Xi'an University of Electronic Science and Technology Press, 1997