Application of Ultra-Large Capacity Storage in Pipeline Diameter

Flash memory is a memory that can be electrically erased and written and does not lose information after power failure (non-volatile). It has the characteristics of low power consumption and fast erase speed, and is widely used in the field of external storage.
As the main means of transporting oil and gas resources, pipeline transportation has received more and more attention for its operational safety. Due to different requirements, the diameters of the laid pipelines are different, and the pipelines will also have various deformations during long-term operation, which has a considerable impact on the operation of pipeline defect detectors and is prone to cause jamming and other consequences. The diameter gauge is an instrument developed to record the changes in pipe diameter. Generally, the diameter gauge runs continuously for hundreds of kilometers, and the corresponding recorded data will reach hundreds of megabytes. 32MB and 64MB flash memory can no longer meet the needs. Therefore, the K9F2G08U0M developed by Samsung was selected, with a single-chip capacity of up to 264MB, which can meet engineering needs.
This article will introduce the main performance of this memory and its application in the pipeline diameter gauge.
1 Introduction to K9F2G08U0M Memory
From the interface point of view, although the capacity and addressing range of K9F2G08U0M far exceed those of common microcontrollers, the write controller on the chip can automatically control all programming and erasing functions, provide necessary repetitive pulses, internal confirmation and data space, and only receive commands and data from the microcontroller through the I/O interface without address lines, so it is very convenient to operate in practice. In addition, the chip increases its capacity through the "NAND" unit structure, so its performance is not weakened; the chip has an independent 1-page data memory and cache memory, so it can complete the page programming operation of 2112B within 0.2ms and the block erase operation of 128KB within 2ms. At the same time, the data in the data area can be read out at a speed of 30ns/B.
The entire storage area is divided into 2 048 independent blocks, and the organizational structure of the blocks can be classified logically and physically.
Figure 1 shows the logical structure of a block. Each block is divided into 64 pages, and each page is 2 112B (2 048B + 64B of additional storage area). The chip accesses each byte through the page address and the byte address within the page. Usually the page address is called the row address, and the byte address within the page is called the column address, that is, 264MB = 2048 blocks × 64 pages/block × 2112 bytes/page = 217 rows × 2112 columns. Therefore, the row address requires 3 bytes and the column address requires 2 bytes. The input order is shown in Table 1.

From the perspective of physical structure, the chip is a "NAND" structure memory. Each block consists of two "NAND" structure strings. Each "NAND" structure string contains 16,896 "NAND" structures. Each "NAND" structure consists of 32 basic units (each basic unit is 1 bit). These 32 basic units are located in different pages, thus obtaining the physical structure of each block, as shown in Figure 2.

2 Hardware connection design
The structural block diagram of the pipeline diameter meter is shown in Figure 3. During pipeline detection, the MCU collects parameters and stores them in the Flash. After the detection is completed, the data is transmitted to the host computer through the USB interface for data analysis.

As mentioned above, the operation of K9F2G08U0M can be realized by sending data (including command code, row and column address code, etc.) to the I/O interface only. Therefore, the most direct way is to use a port of the microcontroller as the data interface with the chip, and connect CE, ALE, CLE and CE with the GPIO pins of the microcontroller. When programming, control these pins according to the timing diagram in the manual. However, since a large number of control line level conversions are required
for each operation of these pins, the program is very cumbersome. Since C8051F020 provides an external memory interface (EMIF), and the interface timing is generated by the EMIF hardware, it is as simple and fast to operate the device expanded outside the chip as to address the memory unit. The following uses this hardware connection method to introduce the main operations of K9F2G08U0M. The circuit is shown in Figure 4. C8051F020 only draws the EMIF interface part, and selects the non-multiplexing method, using IO7~0 as the data line, and CE, ALE, CLE as the address line. Since data needs to be written at any time in the path meter, the write protection terminal is connected to a high level.
When programming a device using an external memory interface, the most important thing is to ensure that the bus timing is consistent with the device timing. The EMIF interface timing of the C8051F020 can be programmed in units of system clock cycles, thus allowing the connection of devices with different setup and hold time requirements and different /WR, /RD strobe pulse widths.

In the non-multiplexed mode of the MCU EMIF, the minimum execution time of an off-chip XRAM operation is 5 SysClk cycles (1 SysClk for or pulse + 4 additional SysClk). If the MCU system uses a 20MHz crystal oscillator, the minimum execution time of a MOVX operation is 250ns, and the upper limit of the minimum setup and hold time in the K9F2G08U0M AC parameters is 100ns, then even if the EMI0TC minimum timing parameters are used, there is no need to add additional delay instructions in the program.
3 Software Design
This system is programmed in C language, which improves the development speed and reduces the difficulty of maintenance. The main operations of the memory are introduced below.
3.1 Read by page
K9F2G08U0M has a 2112B, i.e., 1 page size data register, which determines that the memory read operation is performed in 1 page as the basic unit. As shown in Figure 5, after writing 30H, the data in the page specified by the row address will be transferred to the data register within 25?Zs. Then, under the action of the pulse, not only can it be read continuously from the specified column address to the end of the page, but it can also input the random read instruction code according to the dotted part of the flow chart to read the content of the page at will, and there is no limit on the number of times.

The following is the C language code of the page read operation function.
sbit RdyorBsy=P0^0；
unsigned char xdata * data pK9F；
void PageRead(unsigned int ColAdd，unsigned long
RowAdd，unsigned int len)
{
unsigned int i=0；
unsigned char ColTemp，RowTemp；
ColTemp=(unsigned char)(ColAdd>>8)；
RowTemp=(unsigned char)(RowAdd>>16)；
ColTemp &=0x0F；
RowTemp &=0x01；

pK9F=0x8002；
* pK9F=0x00；
pK9F=0x8001；
* pK9F=(unsigned char)(ColAdd)；
* pK9F=ColTemp；
* pK9F=(unsigned char)(RowAdd)；
* pK9F=(unsigned char)(RowAdd>>8)；
* pK9F=RowTemp；
pK9F=0x8002；
* pK9F=0x30；

while(RdyorBsy);
while(!RdyorBsy);
pK9F=0x8000;
for(i=0; i
OutputData[i]= * pK9F;
}
3.2 Page
Programming When writing data to the device, first write the data into the data register. The device write operation is based on the page, and it is allowed to program the continuous part of a page in one page programming cycle. The continuous part of the same page cannot be programmed more than 4 times.
The device supports random data input within 1 page, which is started by the random input command code 85H, as shown in the dotted box in Figure 6. Multiple random input operations. After the data input is completed, write the page programming confirmation command 10H to write the content in the data register into the storage area. After the writing is completed, it is necessary to read the status register (by writing 70H) to determine whether the operation is successful If the writing fails, the current block should be declared as a bad block and the block data should be replaced to ensure the reliability of the entire system.
In addition, it should be noted that when programming pages within the same block, you must start from the page with the lowest address and move to the next page. The pages with high addresses are programmed sequentially, and the page programming with random page addresses is prohibited.
The following is the C language code of the page programming subroutine.

unsigned char PageWrite(unsigned int ColAdd，unsigned long
RowAdd)
{
unsigned int data i=0；
unsigned char data Status=0；
unsigned char data ColTemp，RowTemp；

ColTemp=(unsigned char)(ColAdd>>8)；
RowTemp=(unsigned char)(RowAdd>>16)；
ColTemp &=0x0F；
RowTemp &=0x01；

pK9F=0x8002；
* pK9F=0x80；
pK9F=0x8001；
* pK9F=(unsigned char)(ColAdd)；
* pK9F=ColTemp；
* pK9F=(unsigned char)(RowAdd)；
* pK9F=(unsigned char)(RowAdd>>8)；
* pK9F=RowTemp；
pK9F=0x8000；
for(i=0；i<2112；i++)
* pK9F=InputData[i]；
pK9F=0x8002；
* pK9F=0x10；

while(RdyorBsy)；
while(!RdyorBsy)；

pK9F=0x8002；
* pK9F=0x70；
pK9F=0x8000；
Status=* pK9F；
Status &=0x01；
return (Status)；
}
3.3 Block Erase
The erase operation is performed in blocks. Since the device is divided into 2 048 blocks, only 11 bits of A18~A2 in the input address code are valid, and the remaining bits will be ignored. The erase is started by entering the confirmation command code to prevent misoperation. The block erase process is shown in Figure 7. The same page programming operation is similar. After the erase is completed, the status register should also be read and the return result should be processed.

3.4 Page Copy
Page copy operation is used to quickly and efficiently move data between pages, because it eliminates the time-consuming read and write operations between off-chip devices. The advantage of this feature is particularly evident when the block replacement operation is used for inter-page data copy. In fact, this operation is a combination of page read and page program operations. The page copy read command 35H moves the data in the page to the data register, and the page copy write command 85H copies the data to the target page. The page copy flow chart is shown in Figure 8.

This operation can also modify the data in the original page and write it to the target page, as shown in the dotted box in flowchart 8.
It should be noted that the page copy operation can only be performed between odd pages or even pages, and the data movement between odd and even pages will be prohibited.
3.5 Buffer area programming
In addition to the data register of 1 page size, the chip also has a buffer register of 1 page size. The buffer register can receive external data while the data register participates in page programming, waits for the data register to be idle to transfer the data, and then continues to receive data. Therefore, the use of buffer area programming operation will greatly improve the efficiency when writing multiple pages of data continuously.
The buffer area programming process is shown in Figure 9. When the first set of data is written to the buffer register, the cache command 15H is written to pass the data to the data register and start page programming, and then the buffer register is idle to prepare for receiving the next set of data. During this process, the chip will be in a busy state. If the internal programming operation is not completed, the duration of the busy state will be extended.

It should be noted that this operation can only be performed within the same block, so when writing multiple blocks of data, it is necessary to pay attention to the last page of each block. If the system only monitors the programming progress through the Ready/Busy pin of the chip, the write operation of the last page should be started by the page programming command 10H. It can also be judged by reading the I/O 5 bit in the status register.
K9F2G08U0M is a new type of ultra-large capacity Flash memory, which is widely used in single-chip embedded systems for its non-volatility, low power consumption and simple operation. In the development process of the pipeline diameter instrument, this paper uses the two control lines ALE and CLE of the memory chip as address lines based on the in-depth understanding of the external memory interface, making the operation of the memory simpler and more efficient. The program in this article has been verified in practice. Due to space limitations, only the code for page reading and page programming is given.