Tempus DRA Suite Accelerates Advanced Node Technologies

In a technology-driven environment, semiconductor design needs to be faster, more energy-efficient, and more robust. To meet this demand, semiconductor manufacturers need to continuously break through technological innovation. By analyzing more parameters and their impact, customers can achieve better PPA goals than current design methods. For example, global ratings or global margins can cause significant waste of performance and power consumption.

To address similar challenges, Cadence continues to innovate and develop the Cadence Tempus Design Robustness Analysis (DRA) suite, which provides the analysis capabilities needed to solve the above problems. The suite uses advanced modeling algorithms to enable engineers to analyze, identify and correct key design elements that are extremely sensitive to changes, including Tempus ECO Options for the module level and Cadence Certus convergence solutions for the subsystem/full chip level, both of which can be called in the Innovus design implementation system. By fully leveraging the advanced analysis features of the suite, customers can enhance design robustness, optimize power, performance and area (PPA) targets, and achieve up to 10% improvement in PPA targets compared to traditional margin-based methods.

Tempus DRA Kit

Tempus DRA suite combines superior analysis capabilities to address design-level robustness issues for different types of timing deviations such as aging effects, voltage drop, and threshold voltage skew. The suite includes five advanced analysis capabilities, each for a specific flow of robust semiconductor design.

1. Aging robustness

Tempus DRA suite is unique in the industry for its excellent aging robustness analysis capabilities, with a PPA target of up to 10%, and is suitable for automotive, aerospace, consumer electronics, mobile devices and large-scale computing. The suite allows engineers to control the aging characterization environment and parameters within the Cadence Liberate Library characterization flow tool, providing complete analysis results of the aging environment and visually presenting stress and recovery status through statistical charts.

Combined with aging-aware timing and constraints, aging robustness can achieve excellent PPA results with SPICE-level accuracy. With the support of TSMC TMI and other SPICE reliability models, static timing analysis (STA), instance aging, non-uniform aging, and recovery model selection in any scenario can be tracked, and the optimal settings of STA can be adjusted. Thanks to this, unnecessary delays caused by aging effects are eliminated, further accelerating design convergence.

2. Voltage robustness

Voltage robustness analysis is seamlessly integrated with the Tempus Power Integrity (PI) and Voltus IC Power Integrity solutions, significantly improving existing signoff solutions. The integration uses a new generation of (IR) voltage drop analysis and repair technology. Voltage robustness analysis automates the repair process through the Tempus ECO Option and solves voltage drop problems by optimizing the Victim and Aggressor signal paths. Notably, this analysis can identify timing violations that are easily overlooked by traditional IR voltage drop signoff methods, preventing the occurrence of costly silicon failures. Reducing the maximum IR voltage drop design margin can also help achieve better PPA goals.

3. Timing robustness

Timing robustness analysis is the third analysis capability of the Tempus DRA suite. This powerful capability can achieve timing accuracy through statistical measurements of silicon performance, significantly improving design PPA while meeting Sigma reliability requirements. Its user-friendly interface can accelerate the design local change (ECO) process and provide a more straightforward approach than traditional SPICE Monte Carlo analysis.

4. Silicon Forecast

Silicon prediction is the fourth analysis capability of the Tempus DRA suite, which focuses on the continuous tuning of silicon characteristics. It can provide fast feedback on the device models, libraries and target device models of silicon wafers, helping design engineers to quickly adjust the design. Silicon prediction supports various stages of design including PBA (physical design, build and analysis), GBA (global build and analysis), and is available in Tempus timing solutions, Tempus ECO Option and Innovus design implementation system.

Design engineers can use silicon prediction to correlate models with hardware to achieve ideal silicon performance, and achieve accurate statistical modeling during Tempus timing and Liberate characterization flows, identifying discrete parameters during pre-silicon static timing analysis (STA) signoff. This analysis capability empowers design teams to achieve confident convergence and optimization, predict delays using silicon prediction, and improve PPA and yield.

5. Voltage threshold skew robustness

Voltage threshold (VT) skew robustness is the fifth analysis capability of the Tempus DRA suite, which addresses the timing pessimism inherent in current STA methods. The Tempus DRA suite helps engineers analyze TT (temperature and voltage) corners more sensitively, performing fast derating for each VT type to optimize delays to slow and fast corners (SSG and FFG). Designers can bind libraries to VT types and define slow and fast derating for each VT type. The Tempus DRA suite can perform optimization permutations and find the worst slack variants based on the launch and capture paths of the VT type.

Tempus DRA Suite is a complete set of advanced analysis capabilities dedicated to enhancing design-level robustness and achieving superior PPA improvements over traditional methods. With its focus on aging robustness, voltage robustness, timing robustness, silicon prediction, and VT skew robustness, the suite helps design teams create more efficient, reliable, and competitive semiconductor solutions in a rapidly iterating technology environment. This is a key step in enabling next-generation semiconductor designs.

The Tempus DRA suite is part of the broader Cadence digital and signoff workflow, supporting the Cadence Intelligent System Design strategy to help achieve superior system-on-chip (SoC) designs. Learn more about the advanced analysis features of the Tempus timing solution.