Applied Materials Launches New Ioniq™ PVD System to Help Solve the Problem of Wiring Resistance in 2D Scaling

SANTA CLARA, Calif., May 26, 2022 – Applied Materials, Inc. has announced a new system that improves the transistor wiring deposition process, significantly reducing resistance and breaking through a major bottleneck facing chips in terms of both performance improvement and power reduction.

The Endura® Ioniq™ PVD system is Applied Materials’ latest breakthrough in solving the challenges of 2D micro-wiring resistance. The Ioniq system is an Integrated Materials Solution™ (IMS™) that combines surface preparation, PVD and CVD processes into a single high vacuum system

Chipmakers are using advances in lithography to shrink chip manufacturing to nodes of 3 nanometers and below . But as interconnects get thinner, resistance increases exponentially, which not only reduces chip performance but also increases power consumption. If this problem is not solved, the benefits of more advanced transistors will be completely offset by the exponentially increasing wiring resistance.

Chip wiring generally refers to the process of depositing metal into trenches and vias etched into dielectric materials. In traditional processes, the metal stack used for wiring deposition usually consists of the following parts: a barrier layer to prevent metal from diffusing with the dielectric material; a liner layer to improve adhesion; a seed layer to promote metal filling; and a conductive metal such as tungsten or cobalt for transistor contacts and copper for interconnects. Because barrier and liner layers are difficult to scale, as the size of trenches and vias decreases, the proportion of space available for conductive materials decreases - the smaller the interconnect, the higher the resistance.

Applied Materials Endura® Ioniq™ PVD System

The Ioniq PVD system is an Integrated Materials Solution™ (IMS™) that integrates surface preparation, PVD and CVD processes into the same high vacuum system. Ioniq PVD provides chip manufacturers with a solution to replace high-resistance titanium nitride liner and barrier layers with low-resistance pure tungsten PVD films, and then use subsequent pure tungsten CVD films to make pure tungsten metal contacts. This solution solves the resistance problem and allows two-dimensional scaling to continue to work at 3 nanometers and below.

“Applied’s latest breakthrough in solving the resistance challenge is an excellent example of how materials engineering innovation is enabling continued 2D scaling,” said Dr. Purab Raja, senior vice president and general manager of Applied Materials’ Semiconductor Products Group. “The innovative Ioniq PVD system breaks a major bottleneck in transistor performance, allowing it to run faster while reducing power losses. As chip complexity increases, the ability to integrate multiple processes in a high vacuum is critical to customers’ ability to improve routing to meet their performance and power goals.”

Endura Ioniq PVD system is currently used by many industry-leading customers around the world. To learn more about this system or other Applied Materials solutions for solving critical routing and interconnect challenges, please attend Applied Materials' "New Approaches to Chip Routing and Integration" master class on May 26, US time.