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This course is offered by Prof. James Chien-Mo Li, Lab of Dependable Systems, National Taiwan University.
Lecture notes available on course website http://cc.ee.ntu.edu.tw/~cmli/VLSItes...
This course is based on the teaching materials of late Professor McCluskey, Stanford University
Chapters
Chapter 1：Introduction What Is Testing (12 minutes and 37 seconds)
Chapter 2：Introduction Types Of Tests (30 minutes and 58 seconds)
Chapter 3：Introduction TestQuality (32 minutes and 9 seconds)
Chapter 4：Introduction Test Economics (33 minutes and 41 seconds)
Chapter 5：ReferenceDedication (_optional) (13 minutes and 16 seconds)
Chapter 6：LogicSim Intro (9 minutes and 37 seconds)
Chapter 7：LogicSim Model (22 minutes and 9 seconds)
Chapter 8：LogicSim CompliedCode (12 minutes and 50 seconds)
Chapter 9：LogicSim EventDriven (26 minutes and 4 seconds)
Chapter 10：LogicSim Parallel (13 minutes and 13 seconds)
Chapter 11：LogicSim Issues (_ optional) (21 minutes and 48 seconds)
Chapter 12：FaultModeling Intro (17 minutes and 23 seconds)
Chapter 13：FaultModeling SSF (15 minutes and 52 seconds)
Chapter 14：FaultModeling BridgeFault (19 minutes and 5 seconds)
Chapter 15：FaultModeling DelayFault (28 minutes and 3 seconds)
Chapter 16：FaultModeling TransistorFault (_ optional) (26 minutes and 49 seconds)
Chapter 17：FaultModeling_ FaultDetect,FaultCoverage (20 minutes and 13 seconds)
Chapter 18：Equivalent Fault Collapsing (18 minutes and 25 seconds)
Chapter 19：Dominance Fault Collapsing, DFC (_optional) (28 minutes and 34 seconds)
Chapter 20：FaultSim Intro (15 minutes and 26 seconds)
Chapter 21：FaultSim Parallel (17 minutes and 0 seconds)
Chapter 22：FaultSim Deductive (21 minutes and 59 seconds)
Chapter 23：Concurrent Fault Simulation (14 minutes and 45 seconds)
Chapter 24：FaultSim DiffFsim (23 minutes and 14 seconds)
Chapter 25：FaultSim Alternatives (32 minutes and 11 seconds)
Chapter 26：FaultSim IssueConclusion (_optional) (8 minutes and 38 seconds)
Chapter 27：Testability Intro (21 minutes and 3 seconds)
Chapter 28：Testability SCOAPseq (_optional) (28 minutes and 15 seconds)
Chapter 29：Testability COP (16 minutes and 49 seconds)
Chapter 30：Combinational ATPG Introduction (14 minutes and 52 seconds)
Chapter 31：Combinational ATPG (Boolean Difference) (21 minutes and 48 seconds)
Chapter 32：Combinational ATPG (Single Path Sensitization) (23 minutes and 34 seconds)
Chapter 33：Combinational ATPG, D_algorithm (33 minutes and 22 seconds)
Chapter 34：Combinational ATPG, CAN (36 minutes and 28 seconds)
Chapter 35：Combinational ATPG, FAN (38 minutes and 4 seconds)
Chapter 36：Combinational ATPG, SAT (8 minutes and 47 seconds)
Chapter 37：Combinational ATPG, acceleration techniques (34 minutes and 33 seconds)
Chapter 38：Sequential ATPG Introduction (16 minutes and 13 seconds)
Chapter 39：Sequential ATPG (9_valued) (11 minutes and 51 seconds)
Chapter 40：Sequential ATPG (Backward Time Frame Processing) (25 minutes and 10 seconds)
Chapter 41：Sequential ATPG Simulation (_optional) (27 minutes and 45 seconds)
Chapter 42：Sequential ATPG Conclusion (_optional) (13 minutes and 14 seconds)
Chapter 43：DelayTest Intro (20 minutes and 38 seconds)
Chapter 44：Delay Test _ Path Sensitize (23 minutes and 38 seconds)
Chapter 45：DelayTest PathTG (26 minutes and 58 seconds)
Chapter 46：DelayTest PathFsim (26 minutes and 30 seconds)
Chapter 47：DelayTest TransitionFsimTG (14 minutes and 44 seconds)
Chapter 48：Diagnosis Intro (20 minutes and 39 seconds)
Chapter 49：Diagnosis StaticCE (28 minutes and 22 seconds)
Chapter 50：Diagnosis DynamicCE (18 minutes and 22 seconds)
Chapter 51：Diagnosis EffectCause (26 minutes and 15 seconds)
Chapter 52：Diagnosis, Chain Diagnosis (_optional) (28 minutes and 45 seconds)
Chapter 53：DFT1 Intro (23 minutes and 22 seconds)
Chapter 54：DFT1 ScanConcepts (21 minutes and 23 seconds)
Chapter 55：DFT1 _ Test Mode Operation (SSF & Delay Test LOS_LOC) (25 minutes and 49 seconds)
Chapter 56：DFT1 Muxed_D Scan ATPG model (_optional) (28 minutes and 19 seconds)
Chapter 57：DFT1 ClockScan (_optional) (13 minutes and 31 seconds)
Chapter 58：DFT1 LSSD (11 minutes and 58 seconds)
Chapter 59：DFT1 ScanDesignFlow (36 minutes and 0 seconds)
Chapter 60：DFT1 IssueSol (26 minutes and 52 seconds)
Chapter 61：DFT2 JTAG Intro (15 minutes and 38 seconds)
Chapter 62：DFT2 JTAG Registers (21 minutes and 46 seconds)
Chapter 63：DFT2 JTAG Instruction (20 minutes and 40 seconds)
Chapter 64：DFT2 JTAG Instruction (old version) (20 minutes and 59 seconds)
Chapter 65：DFT2 Instruction2Conclude (15 minutes and 21 seconds)
Chapter 66：BIST1 Intro (20 minutes and 39 seconds)
Chapter 67：BIST1 LFSR (36 minutes and 49 seconds)
Chapter 68：BIST1 _ LFSR seed solving (26 minutes and 24 seconds)
Chapter 69：BIST1 LFSRpolynomial (29 minutes and 23 seconds)
Chapter 70：BIST1 CA (29 minutes and 28 seconds)
Chapter 71：BIST2 Intro (26 minutes and 6 seconds)
Chapter 72：BIST2 SerialORA (41 minutes and 25 seconds)
Chapter 73：BIST2 Parallel ORA MISR (30 minutes and 15 seconds)
Chapter 74：BIST2 Architecture (16 minutes and 41 seconds)
Chapter 75：BIST2 Design Phase Shifter for LFSR TPG (10 minutes and 29 seconds)
Chapter 76：BIST2 IssuesConclude (_optional)_2 (34 minutes and 36 seconds)
Chapter 77：TestCompress Intro (21 minutes and 17 seconds)
Chapter 78：TestCompress SoftwareSTC (37 minutes and 26 seconds)
Chapter 79：Test Compress Hardware Stimulus (updated 5_10_2020) (28 minutes and 8 seconds)
Chapter 80：TestCompress HardwareResponse (_optional) (29 minutes and 49 seconds)
Chapter 81：MemTest Intro (32 minutes and 24 seconds)
Chapter 82：Memory Test _ Classical algorithm (23 minutes and 41 seconds)
Chapter 83：MemTest March (25 minutes and 17 seconds)
Chapter 84：FunctionTest Intro (19 minutes and 31 seconds)
Chapter 85：FunctionTest CheckExp (37 minutes and 51 seconds)
Chapter 86：FunctionTest IOV (34 minutes and 56 seconds)
Chapter 87：FunctionTest SV (_optional) (15 minutes and 55 seconds)
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