Synopsys Solutions Qualified by Samsung for 5nm, 4nm, and 3nm Processes

Synopsys' PrimeLib Unified Library Characterization and Verification Solution Qualified by Samsung for 5nm, 4nm, and 3nm Processes

Based on this solution, mutual customers of both parties can) recently announced that Samsung Foundry (hereinafter referred to as "Samsung") has certified Synopsys' PrimeLib™ unified library characterization and verification solution in 5nm, 4nm and 3nm process technologies to meet the advanced computing needs of next-generation designs such as high-performance computing (HPC), 5G, automotive, hyper-connected, aerospace, and artificial intelligence (AI) chips. The certification also includes the verification of PrimeSim™ Continuum, which provides the foundation for the integrated simulator technology embedded in the Synopsys Custom Design Platform and PrimeLib solutions, providing developers with a seamless simulation experience to help them achieve golden quality sign-off.

With each process node evolution, the computational requirements increase by 3 times, and the complexity of library characterization increases significantly. The key feature of the PrimeLib solution is that advanced machine learning (ML) algorithms and adaptive flows generate accurate statistical variation models nearly 5 times faster than previous generations at ultra-low voltage corners, while reducing overall computational costs. This next-generation solution also includes innovative SmartScaling technology for multi-PVT characterization, which can achieve instant library generation at the minimum characterization corner based on the Synopsys PrimeTime® extension engine.

"We are committed to providing our customers with the most innovative technology solutions to address the increasingly challenging design and complex modeling challenges at 5nm and below," said Sangyun Kim, vice president of Samsung Foundry. "Synopsys' PrimeLib library characterization and verification solution enables us to deliver high-quality signoff libraries for advanced nodes 5x faster, helping our mutual customers accelerate the overall chip design process and tapeout to achieve their desired power, performance, and area (PPA) targets."

To meet the market's growing demand for chip performance optimization, high-quality libraries for advanced process nodes, and system design on the cloud, the accuracy requirements of 5nm to 3nm processes require efficient library characterization cycles for advanced models, such as electromigration (EM), aging, and free variation format (LVF). Other overall variations for next-generation applications will result in changes in process, voltage, and temperature (PVT), which will significantly affect chip design. These changes will ultimately lead to increased computing pressure, that is, a large amount of support will be required during peak demand for process design kit (PDK) changes, causing delays in design delivery time.

PrimeLib library characterization supports advanced models such as transient LVF, aging and EM, and provides exclusive simulator license support for the characterization and high scalability of existing solutions by providing up to 5 times faster turnaround time (TAT) for more than 10,000 parallel jobs in the cloud or computing group. By leveraging the embedded PrimeSim SPICE and HSPICE engines and integrating verification capabilities, the PrimeLib solution can also create PrimeTime gold quality sign-off libraries and PrimeShield® design stability analysis.

PrimeLib key product features and benefits include:

ML model, with up to 5 times LVF performance improvement, can accurately calculate ultra-low PVT corner effects. It can provide cloud support and adopt excellent expansion technology to effectively handle various workloads while reducing TAT from weeks to days;

SmartScaling technology for multiple PVT corners reduces characterization run times by 3 to 10 times and enables instant library generation;

The embedded PrimeSim SPICE engine and signoff verification capabilities combine to create PrimeTime gold-quality signoff libraries, dependencies, constraints, and power verification;

Enhanced ML-based sensitivity database reduces time-to-market for upgraded PDKs.

"Successful IC designs require high-quality libraries, and Synopsys' PrimeLib provides a comprehensive set of capabilities that enable customers to confidently scale with evolving industry requirements," said Sanjay Bali, vice president of product marketing for the Digital Design Group at Synopsys. "We have a long-standing collaboration with Samsung to deliver best-in-class process technologies, and this certification is the result of our continued innovation and will accelerate high-performance designs for our mutual customers."