RISC-V Foundation CTO: Standing on the shoulders of giants, looking forward to the next decade

Author: Mark Himelstein, CTO of RISC-V Foundation

RISC-V is now a decade old. Here’s a look at what the RISC-V Foundation has accomplished and how it’s moving forward with extensions targeting specific computing environments and industries.

The RISC-V Foundation is developing a series of optional extensions designed to support specific industries, as well as the computing industry as a whole, in new and unprecedented ways.

This article provides three examples of these extensions: safety, vectorization, and reduced code size.

RISC-V recently celebrated its 10-year anniversary, and our community is now in a unique position to leverage its previous history in open source software and hardware.

RISC-V is a complete open source architecture that fully embodies the characteristics of RISC. It is a flexible platform suitable for solutions that address a variety of industry needs, from the Internet of Things (IoT) to supercomputers.

We initially developed a compact instruction set architecture (ISA) that was able to include common, optional, and custom extensions. Not surprisingly, the bar is much higher now than it was in the 1980s when the first commercial RISC chips appeared, which means higher requirements for ISA features and a growing ecosystem to produce deployable products.

Of course, the ISA is just the tip of the iceberg. It is not useful on its own, so we have and are continuing to develop a rich software ecosystem, ensuring that tools and capabilities (e.g., simulators, verification tools, operating systems, hypervisors, debuggers, compilers, etc.) are in place. In turn, RISC-V members can benefit from the joint efforts with the community and accelerate innovation.

Our organization is developing a range of optional extensions designed to support specific industries, as well as the computing industry as a whole, in new and unprecedented ways. The three examples I'll discuss here are cryptography, vector processing, and reducing code size.

Safety

Regardless of industry or implementation, companies must decide what level of security their applications require. This is one of those situations where things have changed a lot since the beginning of RISC, from the need to use improved encryption standards like AES to protection against malicious attacks like Spectre and Meltdown.

For example, the RISC-V Cryptography Task Force has designed many instructions that belong to other extensions (such as RISC-V’s bit manipulation extensions) and is designing crypto-specific extensions. So if the financial sector needs to protect every transaction, the extensions we’ve defined could reduce the instructions required for AES-128 encryption by more than an order of magnitude (from 1145 instructions to 78 instructions in a 64-bit RISC-V design). Using RISC-V’s vector extensions, high-performance implementation techniques can further reduce the number of instructions to less than one instruction per block, while improving resistance to side-channel attacks. The RISC-V organization is very frugal with what it allows in the ISA, and task forces must demonstrate the value of extending the instruction set to the community before they choose to do so.

Vector Processing

Vector processing has been around for a long time, ever since the days of ILLIAC or CRAY I. It has always been used by key sectors such as weather forecasting and sonar. However, now with the rise of Artificial Intelligence (AI) and the proliferation of Machine Learning (ML) in all types of applications and solutions, the need for vector processing has become mainstream.

RISC-V has the advantage of history. We have seen all the implementations that have come out and the needs of modern applications and workloads. So we have a group of architects in the community designing vector extensions to handle the most demanding uses, like sparse matrices, etc.

Furthermore, because we created vector extensions without the burden of history and with a holistic view, we noticed exactly what was needed. For example, for the memory system, to reduce the impact of those very sparse matrix operations, we added virtual memory (such as page tables and tlbs) and memory access (support implementations to effectively reduce cache impact on traversal operations).

Reduce the amount of code

Embedded operations, such as IoT applications and computer equipment, often require code size reduction. We created a C extension that supports 16-bit instruction versions of the corresponding instructions in the 32-bit standard instruction set. As you can imagine, this reduces space requirements and improves cache locality.

However, once we designed the C extension, it became clear that all other segments could take advantage of this extension to enhance their cache locality. Subsequently, the C extension became the base extension that most implementers would include in their designs. But we didn't stop there. We looked at the needs of the embedded market holistically and came up with other extensions, such as one called Zfinx. It allows implementers to share registers between integer and floating point operations, reducing the space required for registers.

Through these examples, you can see that RISC-V is taking the needs of specific industries into account and translating them into appropriate RISC-V features. Such a holistic view coupled with the flexibility of RISC-V has attracted members from a wide range of industries. We intend to continue this pattern. As a result, one day you may see RISC-V designs in your toaster, as well as the largest supercomputer on Earth, and in every computing platform in between.