Huami releases Huangshan 2S chip: dual-core RISC-V architecture, power consumption reduced by 56%

According to Jiwei.com, this afternoon, Huami Technology held the Next Beat conference, where it officially released its self-developed new generation wearable chip Huangshan 2S.

Huami said that Huangshan 2S is the first wearable AI processor to adopt dual-core RISC-V architecture. Its super-powerful core computing performance can support high-load computing such as graphics and UI operations. The large-core system also integrates FPU to support floating-point operations. Compared with Huangshan 2, Huangshan 2S has an 18% increase in computing power, a 56% reduction in operating power consumption, and a 93% reduction in sleep power consumption.

In terms of specific hardware specifications, Huangshan 2S integrates a 2.5D GPU, which can improve the graphics acceleration performance by 67% compared to Huangshan 2. It is equipped with a convolutional neural network acceleration processing unit that can quickly identify disease types. Taking atrial fibrillation as an example, its recognition speed is 26 times that of pure software calculation. It was successfully taped out in March this year and will become one of the core chips of the third-generation Amazfit smartwatch.

At the press conference, Huang Wang, founder, chairman and CEO of Huami Technology, also reviewed Huami's journey of self-developed chips: it began to deploy upstream and downstream chip industries in 2015, invested in SiFive, which invented the RISC-V open source instruction set in 2018, and in September of the same year, Huami independently developed the world's first artificial intelligence chip in the field of smart wearables, Huangshan No. 1, and in June 2020, it updated the Huangshan No. 2 with better performance and power consumption.