CompactPCI Express Hybrid Bridge Board Design

0 Introduction

In the past few years, as the requirements for data input/output continue to increase, users have put forward higher requirements for data bus bandwidth, resulting in the emergence of many transmission standards based on high-speed serial architecture, including PCI Express, HyperTransport, InfiniBand, RapidIO and Star-Fabric.

In the second quarter of 2002, PCISIG released the PCI Express 1.0 specification, which was designed as a system interconnection interface. In the third quarter of 2005, the organization released the PCI Express specification for industrial control, PICMG EXP. 0 CompactPCI Express Specification R1.0, which is called the CompactPCI Express (hereinafter referred to as CPCIe) specification.

The CPCIe system is compatible with the CPCI module. The specific implementation method is to add a CPCIe to CPCI bridge module in the system. This module is called a hybrid bridge module.

The design of the hybrid bridge circuit mainly implements the following contents:

(1) Design and implementation of some PCI interfaces;
(2) Design and implementation of PCIe bus interfaces.

1 Design Principle

As shown in Figure 1, the module is connected to XSJ4 to provide 3.3 V power supply. A DC-DC voltage conversion module is used on the board to convert the 3.3 V voltage to 1.5 V voltage, which is provided to PEX8111. The upstream port (Upstream) of PEX8111 is a x1 PCI Express interface, and the downstream interface (Downstream) is a 32-bit/33 MHz PCI bus. This PCI interface can realize the host function of the PCI bus.

2 Implementation Method

2.1 Selection of main components

In this design, mature technology is adopted, common and reliable control chips are selected, and some common peripheral circuits and special circuits are combined to realize all functions. That is, PEX8111 is selected as the interface chip, and the functional chip is used to realize the hardware logic.

PEX8111 is a chip launched by PLX that is specially used for bridging between PCI Express and PCI bus. It contains one x1 PCI Express port and one 32-bit PCI interface. It has few peripheral circuits and simple design.

2.2 PCI Express Hardware Interface Implementation

Each PCI Express port includes two signals, port control signals and communication signals. Port control signals include hot-swap control signals, clock enable signals, power enable signals, etc. Communication signals are mainly composed of lane channels. Each lane channel contains one pair of transmit and receive differential signals. The number of lane channels contained in each PCI Express port can be scalably configured, that is, the number of lane channels contained is variable. In this module, a single port contains 1 lane channel. High-speed differential signals are transmitted on the lane channel, and the highest transmission rate of the signal on each signal differential pair can reach 2.5 Gb/s. The lane channel interconnected between two devices needs to add capacitors to isolate DC signals. Considering the frequency of the transmission signal, the package size of the capacitor is generally 0402. The small size can reduce the series equivalent inductance of the capacitor and improve the performance of the capacitor in the high-frequency signal area.

2.3 Clock Design

The transmitter outputs data at a rate of 2.5 Gb/s. The clock to achieve this rate must be accurate within ±300 ppm of the center frequency, and it allows a maximum deviation of 1 clock per 1,666 clocks. There are two ways for the device to obtain clock input: using the board clock and using an external input clock. This design uses an external clock. If the spread spectrum clocking (Spread Spectrum Clocking, SSC) function is used, it is generally required that the transmitter and receiver on the link must use the same reference clock. SSC is a technology used to slowly modulate the clock frequency in order to reduce EMI radiation noise at the center frequency of the clock. With SSC, the radiated energy will not generate a 2.5 GHz noise spike signal because the radiated energy is dispersed into a small frequency range around 2.5 GHz.

This module needs to provide a clock signal for an external PCI device, as shown in Figure 2. The 33 MHz crystal is used as the clock source, and 5 clocks are output through the zero-delay buffer CY2305, which are used as the clock sources for PEX8111 and 4 external PCI devices respectively. The zero-delay buffer is a device that can fan out multiple clock signals from one clock signal and make these outputs have zero delay and very low skew, so it can be considered that the 4 external PCI devices work under the same clock.

2.4 PCI interface design

The function implemented by this PCI interface is the PCI HOST function, including bus signals and arbitration signals. When designing this module, it is necessary to pay attention to the fact that the signal definition of connector J1 is slightly different from that of the standard J1 interface. Because if the PCI bus signal is to be fully led out, two connectors J1 and J2 need to be used together, but because the high-speed connector XSJ3 is located at the original position of J2, the complete PCI host function cannot be realized in the absence of some signal pins. The special CPCIJ1 connector is used to solve this problem. This connector has 15 more signal pins than the ordinary J1 connector, and these extra pins can be used to lead out REQn and ACKn signals.

2.5 Power Supply Design

The PEX8111 chip requires three power supplies. The PCI bus signal is 5 V, the I/O power supply voltage is 3.3 V, and the serial transceiver power supply voltage is 1.5 V, so this module needs to provide three voltage sources: 5 V, 3.3 V, and 1.5 V.

5 V and 3.3 V voltages are provided by the system, and 1.5 V is obtained by converting the 3.3 V voltage. The LP2992 of National Semiconductor is selected as the 3.3-1.5 V voltage conversion module. This module has the characteristics of more than 90% conversion efficiency, simple peripheral circuit, smaller package, and ripple voltage below 2.5%.

2.6 Reset Design

There are three reset inputs: the reset from the PCIe side, the reset output from the PEX8111, and the manual reset signal, which ensures that the reset signal can be passed down in the event of a cold reset on the host side and a separate reset of this board is required, as shown in Figure 3.

3 High-speed circuit design

Circuits based on the CPCIe bus are high-speed circuits. Simulation tools are used to verify the circuits at the beginning of design, and the designs are continuously adjusted based on the simulation results.

The key point of this design is to simulate the designed circuit. The types and numbers of PEX8111 chip signals are relatively small. There is no complex logic design on the periphery of the chip. The requirements for clock and power supply in circuit design are also relatively simple. However, there are high requirements for the quality of high-speed differential signals transmitted on PCB. This requirement is also a common problem faced by all current high-speed designs. Since there are many factors to consider in high-speed PCB design, such as medium, plane division, equal length of signals, etc., traditional design criteria are no longer accurate, so simulation tools are needed to provide a design basis. The simulation tools used in this design are Mentor's Hyperlynx GHz, Hspice simulation model, provided by the device manufacturer.

The simulation process mainly includes pre-simulation and post-simulation. The specific contents of the two simulations are described below.

3.1 Impedance Control

The PCI Express specification requires that the trace impedance be 100 Ω, and the differential impedance and single-ended impedance be 50 Ω. Impedance is mainly determined by line width, line spacing, copper thickness, dielectric layer thickness, dielectric material, etc. The characteristic impedance calculation interface is shown in Figure 4. The calculated characteristic impedance is 94.5 Ω, which meets the requirements.

The characteristic impedance of PCI signal is 75 Ω. In order to meet the impedance requirements of PCIe and PCI at the same time, two methods can be used. First, the widths of the two signal lines can be set to different widths; second, the two signals can be placed on different signal planes. Both methods have their own advantages and disadvantages. The former has a lower limit on the line width due to the manufacturing process, so the PCIe signal line width needs to be set wider, which is not conducive to routing. The latter requires adding signal layers, which directly increases costs. Which method to take requires comprehensive consideration.

3.2 Implementation of post-simulation

Post-simulation is mainly to import PCB-related data after the PCB is drawn, and then perform simulation based on pre-simulation. Since the signal circuit design of the PCI part is very mature, there are a lot of empirical rules that can be borrowed, and the signal speed is relatively slow, this part of the signal is not simulated, and only the PCIe differential signal pair is simulated. Figure 5 shows the simulation results of the eye diagram of the receiving end after importing the PCB parameters. It can be seen that the signal voltage at all time points is within the range that the receiver can recognize.

4 Conclusion

With the development of technology, modules based on CPCIe bus interface will be used more and more, but considering the cost, the modules with CPCI interface will not be completely replaced immediately, and the coexistence of CPCIe module and CPCI module in the chassis will exist for a long time. The hybrid bridge module is the link between the two, and it will be widely used as an important plug-in module in industrial control computer systems.