AT91 Series ARM Hardware Design Notes

Power Issues

1.VDDCORE and VDDIO pin power supply

A) The VDDCORE and VDDIO pin supplies must be connected to a clean DC power supply using decoupling capacitors; the decoupling capacitors should be as close as possible to the VDD and GND pins of the microcontroller; the typical value of the decoupling capacitor is 33nF to 100nF.

B) There are no special requirements for the timing of the power supplies, except that the reset delay time is greater than the rise time of the two power supplies.

C) It is important to note that VDDIO power supply cannot be stopped while VDDCORE is still powering the microcontroller to preserve the internal RAM and register contents, if this is done it will not be destructive, but it can cause the inputs of the internal peripherals to go into an undefined state. Furthermore, the current consumption of VDDIO depends on the load capacitance of the I/O lines connected to the EBI and the PIO lines when they are switched, in addition to the resistive load in the continuous state of the current. This means that it is not necessary to stop VDDIO when the CPU is in standby mode.

2. VPP pin

VPP is used to increase the programming and erasing speed of FLASH. For the voltage range, refer to the data sheet. The VPP pin can be disconnected. To prevent accidents, consider applying a known voltage level to prevent unnecessary actions.

Master clock pin

1.MCKI pin

The MCKI pin is the main clock input pin of the microcontroller. This pin inputs a square wave clock signal. The high half cycle (tCH) and low half cycle (tCL) of the external clock have a minimum value, see the data sheet. The AT91X40X series does not have an internal oscillator, so simply connecting a crystal oscillator is not possible.

2.MCKO pin

The MCKO pin provides a delayed mirror image of the clock input signal of the MCKI pin for use by other devices in the system. The MCKO drive capability is low and it is not feasible to use it to drive several TTL loads. When using the AT91X40X series microcontrollers in the BGA package, if this pin is not used, it is strongly recommended that you use it as a test point on the PCB. This can be used to quickly determine whether the microcontroller has a correct clock

NRST input pin

The NRST pin is used for the main system reset. It resets all internal device registers, the program counter of the ARM core and the JTAG/ICE port when it is low. It samples the BMS and NTRI pins during system boot. NRST must be held until the power supplied to the microcontroller is stable and according to the start-up time of the external oscillator.

Before releasing the NRST pin, the 0 level must be maintained for at least 10 clock cycles in order to correctly sample the BMS and NTRI pins.

Pins sampled during reset

1. Boot mode select pin (BMS)

The P25/BMS input pin is sampled on the rising edge of the NRST pin. This pin enables the ARM7TDMI core to start reading instructions from its internal flash memory, or from one or more flash memories connected to the EBI's Chip Select 0 (NCS0). Once the BMS pin has been sampled during reset and the processor has initialized correctly, the P25/BMS pin can be used as a general purpose I/O pin.

Depending on the level of the BMS pin, the boot memory data bus width can be selected, 8 bits or 16 bits. Please refer to the data sheet for details.

2. Three-state input pins

For debugging convenience, the AT91X40X series provides a tri-state mode. This enables the connection of an emulation probe from the target board to the application board. In tri-state mode, all output drive pins of the AT91X40X series microcontrollers are disabled. For the flash-based AT91FR40X series microcontrollers, tri-state mode enables the programmer to treat the microcontroller like an ATMEL flash memory.

When the user does not use the tri-state mode of the AT91 series, the NTRI pin must be pulled up through a 400KR resistor during reset. Note that the NTRI pin is multiplexed as I/O line P21 and TXD1 pin of USART1. If this pin is connected to a standard RS232 driver with an internal 400KR resistor, a pull-up resistor is not required. See RS232 Driver for details. JTAG/ICE Port Pins

In any ARM processor with IEEE1149 standard JTAG/ICE port, TDI, TDO, TMS and TCK are the minimum pins. All pins except TDO pin have internal pull-up resistors of about 10KR.

These pins are used to access the ICE of the ARM core for debugging. The ATX40X series does not have a boundary scan feature in the digital I/O unit, so the boundary scan feature of JTAG cannot be used in this series.

PIO Pins

1. Multiplexing pins

Most of the I/O pins are multiplexed with one or two internal devices. Most of these pins rearrange their states in PIO mode, for example, for example, P21/TXD/NTR1 is not driven by an internal device. Some other pins like address lines A20-A23 have their own states arranged in peripheral mode, for example, driven by EBI. If these pins are not driven by a peripheral device after reset, they act as general purpose I/O pins.

Unused pins do not need to be connected, but in order to avoid unwanted behavior caused by some external abnormal signals and/or additional current consumption caused by internal oscillation, it is usually considered to set these unused pins to output mode in the initialization code. These I/O lines do not have pull-up or pull-down resistors in the embedded microcontroller.

2. Single-function PIO pins

Single-function PIO pins are I/O pins that are not multiplexed with any internal device. By default, all I/O pins are in input mode after reset. Unused I/O pins can be left unconnected but must be set to output mode in the initialization code. These I/O lines do not have pull-up or pull-down resistors in the embedded microcontroller.

1. Address line pin

The AT91X40X series address bus has 24 address lines and can therefore access 16M of memory space. Address lines A0-A23 cannot be multiplexed with any PIO lines or internal devices. Address lines A20-A23 are multiplexed as PIO lines and four additional 4 chip select lines. If these 4 high 4-bit address lines are not used when accessing devices, they can be used as chip select lines or PIO lines. When using the flash-based AT91X40X series microcontrollers, note that address line A20 must not be used as a chip select line (CS7) or PIO line after reset. A20 is the MSB (most significant bit) of the internal flash memory.

2. Data bus pins

The AT91X40X series data bus can use 8-bit or 16-bit mode, depending on the state of the BMS pin for chip select line 0 (NCSO) and the configuration of the EBI chip select register for all other chip select lines. It should be noted that the data bus of the AT91X40X series microcontrollers does not have internal pull-up or pull-down resistors. It is strongly recommended that you add pull-up or pull-down resistors of about 100KR to prevent unexpected behavior caused by external interference signals and/or additional current consumption of VDDIO and VDDCORE caused by internal oscillator failure. The load capacitance that the AT91's EBI data bus can drive can be estimated using the AT91 EBI Timing Calculator application note.

3. Control signal pin

The control bus has several mode read and write lines, chip select lines and byte select lines, which enable users to connect a variety of memory and peripheral devices. Note that, depending on the master clock of the microcontroller, the maximum load capacitance of the NWR and NRD lines must be within the acceptable range. Overloaded NWR and NRD lines can extend some EBI delays, resulting in inconsistent read or write accesses.

The load capacitance that the control bus signals can drive can be estimated using the AT91 EBI Timing Calculator Application Note.

4.NWAIT pin

The NWAIT pin can add additional wait cycles to a read or write access at any time during an access or when the standard wait states are not sufficient. When the NWAIT pin is detected as low, the core clock is stopped and the EBI stops the current access but does not change the output signals or internal counters and states. When the NWAIT pin is released again, the core clock is started and the EBI ends the access operation.

The NWAIT pin input is active low and is detected on the rising edge of the master clock. The NWAIT input signal can only be activated synchronously during the master clock low phase.

The NWAIT signal must also ensure that the setup time and hold time required match on the rising edge of the clock. When the setup and hold times do not match, it can freeze the EBI signals to their active state immediately (or even after a few cycles) and keep this state until a hardware reset is performed. If the NWAIT pin is driven by an external device like a DSP or FPGA, the user must ensure that the NWAIT pin is driven high when the AT91 microcontroller is powered on. If the NWAIT pin is not used, a 100KR pull-up resistor must be added.