ARM Cortex-M branch instruction encoding-EEWORLD

Collect

B. -- Branch causes a branch to a target address

if ConditionPassed(cond) then
{

EncodingSpecificOperations(PC, lable);

BranchWritePC(PC + imm32);

}

// All versions of the Thumb instruction set

T1 : B : not allowed in IT block

T2 : B : outside or last in IT block

// All versions of the Thumb instruction set from Thumb-2 onwards.

T3 : B.W : not allowed in IT block

T4 : B.W : outside or last in IT block

Specifies the label of the instruction that is to be branched to.

The assembler calculates the required value of the offset
from the PC value of the B instruction to this label,
then selects an encoding that will set imm32 to that offset.

Allowed offsets are even numbers in the range

T1 : -256 to 254 : imm8

T2 : -2048 to 2046 : imm11

T3 : -1048576 to 1048574 : imm6 + imm11

T4 : -16777216 to 16777214 : imm10 + imm11

BX -- Branch and Exchange causes a branch to an address and instruction set specified by a register.

T1 : BX // Outside or last in IT block

BLX (register) -- Branch and Exchange calls a subroutine at an address and instruction set specified by a register.

T1 : BLX // Outside or last in IT block

BL, BLX (immediate) -- Branch with Link (immediate) calls a subroutine at a PC-relative address.

T1 : BL // Outside or last in IT block

T2 : BLX // Outside or last in IT block

Keywords：ARM Cortex-M Reference address：ARM Cortex-M branch instruction encoding

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