Design of High Performance LDO Linear Regulator

O Introduction

Power management system has become a hot spot in the current development of the integrated circuit industry and is also an indispensable technology. Without power management, many markets will not exist. Power management can make many markets such as mobile phones, laptops, remote control TVs, and reliable telephone services a reality. Nowadays, electronic products have been popularized in all aspects of work and life, with higher and higher performance-price ratios and stronger and stronger functions, and the power supply circuit is becoming more and more important in the whole circuit.

If the power system is not designed properly, it will affect the architecture of the entire system, the combination of product features, component selection, software design, and power distribution architecture. How to ensure the stability of LDO under different current loads is a challenge for LDO design. To this end, this article proposes an LDO and uses smooth pole following technology to solve the stability problem caused by pole offset under different current loads, thereby improving PSRR. At the same time, its overvoltage protection circuit also effectively prevents the problem of excessive output supply voltage of LDO.

1 Circuit Design

Figure 1 shows the circuit structure of the LDO in this design. The basic structure of this LDO consists of 4 stages, and mainly uses the negative feedback loop composed of the error amplifier A1, the voltage amplifier A2, the voltage buffer A3, the voltage adjustment tube MP1 and the feedback network to maintain the stability of VOUT. Miller capacitor C1 is used to compensate the frequency of the circuit. The bandwidth of the second and third stages should be large to ensure that the LDO is in a stable state. At the same time, it should also be ensured that the output resistance of the adjustment tube remains unchanged under a wider frequency band in order to obtain better power supply rejection performance. If A2, A3, and A4 are simplified into one , then the LDO gain bandwidth of a two-stage Miller compensated operational amplifier can be expressed as:

Where gm1 is the transconductance of A1. As can be seen from the above formula, the gain bandwidth does not change with the change of load capacitance. Its main pole P1 can be expressed as:

Rol is the output resistance of A1, similar to the op amp with two-stage Miller compensation. It is generally hoped that the combined second-stage amplifier is a single-pole system. Due to the pole separation introduced by Miller compensation, the secondary point P2 can be approximately expressed as:

Where is the transconductance of, and gm4 is the transconductance of A4. In order to keep the secondary point at the output node, the output poles of the second and third stages must be pushed to a much higher frequency than the secondary point. In order to ensure its stability, the secondary point needs to be kept at the output node.

For a high-gain system with internal Miller compensation, Miller compensation can better control its stability within a larger load capacitance range, and it will also provide a better transient response. This is because a high-frequency negative feedback formed by the Miller capacitor can be directly coupled to the output, and high gain can achieve better DC and load modulation. However, test results show that the LDO will have an adjustment of about 50 mV when the load current changes significantly. This is because the performance of DC load modulation is limited by the parasitic capacitance of the bonding wire, and the DC IR drop will directly deteriorate the DC load modulation through the parasitic capacitance.

The output current of the LDO is required to be from 0 to full load (100mA in this design), so gm4 will also change with the load current, causing the secondary point P2 to change with the load current. The smooth pole technology can be used to solve this problem during design. For the circuit composed of R and MP2 in series, it can be biased dynamically according to the change of load current. Under large load current conditions, R and MP2 can bias a larger current to widen the circuit bandwidth, while reducing the output resistance to adapt to the secondary point P2 being pushed to a higher frequency. Under small load current conditions, P2 is at a lower frequency, and R and MP2 are biased at a narrower bandwidth and a larger resistance to ensure its stability. The static bias current should be as small as possible to ensure low power consumption of the circuit.

The gate of the adjustment tube can be designed to have a significantly greater resistance to ground than to VDD, so that the gate of the adjustment tube can follow the change of the power supply, thereby obtaining better power supply suppression. In order to produce a smaller resistance to VDD, R and M can be connected in series between the gate and VDD. If the load current of the LDO is very small, then the adjustment tube will work in the weak inversion or subthreshold region, so the Vcs of MP is less than Vth. Since the Vcs of MP and MP are equal, MP is turned off. In this case, R is biased by the N tube of the previous stage circuit. When the load current of the LDO is very large, the Vcs of the adjustment tube increases, MP turns on, and is turned on in series with R with a very small resistance. At this time, MP behaves as a switch. At this time, the resistance of the adjustment tube gate to VDD will be greatly reduced, and the bias current of the previous stage will increase, and the bandwidth will also increase. From the perspective of loop stability, it allows the LDO to adapt to changes in load current by dynamically changing the bandwidth and resistance at the gate of the adjustment tube, thereby better improving
the transient response of the circuit.

2 Overvoltage protection

When the output power supply voltage of the LDO is higher than a certain value, the overvoltage protection circuit will automatically start and adjust the power supply voltage; when the power supply voltage returns to the normal range, the protection circuit will automatically shut down. Figure 2 shows the structure of the overvoltage protection circuit. It should be noted that the adjustment tube of the protection circuit needs to discharge large currents, so it needs special processing on the layout.

3 Simulation Results

This chip is designed and taped out using SMIC 0.18μm CMOS Logic process. The chip area is 170x280μm, the static current is 200μA, and the capacitor is implemented using MOM. Its overall layout is shown in Figure 3. Most of the layout is for power tubes and Miller capacitors. The output power line should be as wide as possible, and multi-layer metal can be used to reduce line resistance.

4 Conclusion

When the load current increases from 0 to 100 mA, the transient characteristic voltage ripple of the LDO designed in this paper is below 50 mV, and the adjustment time is about 20 μs. At the same time, the PSRR of the LDO can reach 63 dB at low frequency and 35 dB at 100 kHz, which can fully meet the system requirements.