Improving power density of switch-mode power supplies in data center servers through packaging and cooling technologies

Introduction

The rapid growth of industries such as cloud-based computing, artificial intelligence, and blockchain has greatly increased the global demand for data center processing power, coupled with rising electricity and space costs, which has driven the need for high-efficiency switch-mode power supplies (SMPS) for the server market that save both power and space. This article will analyze the important role that packaging plays in meeting power and density requirements in server power supplies using silicon and wide bandgap (WBG) switching topologies. It will also briefly introduce the application and development trends of server SMPS, and then discuss component implementation, thermal performance, and the advantages of using Infineon low parasitic inductance surface mount device (SMD) packaging in high-frequency operation.

Server power topology architecture

Contemporary high-efficiency power supplies typically use a totem pole stage to implement bridgeless power factor correction (PFC), and then use an LLC circuit to implement a resonant DC-DC converter (see Figure 1). Typical specifications for server power supplies are Vin = 180 ~ 277V, Vout = 48V, and Pout = 3kW.

Figure 1

Figure 1

Pareto optimization can be used to help understand how the trade-off between operating efficiency and power density is achieved in a converter system. This approach uses a more detailed system and component model when considering different design variables. The efficiency is calculated at 50% rated output power and the losses of the PFC and LLC stages are taken into account. The results of the Pareto optimization calculation of the complete server power system are shown in Figure 2. It shows that the efficiency of the medium power density (~40W/inch3) power supply can reach 98.2%, while the efficiency of higher density designs (greater than 80W/inch3) is slightly lower, with a maximum of 97.5%. A very interesting observation is that in higher density designs, the LLC stage needs to increase the switching frequency, which confirms the packaging requirements when supporting such high density designs.

Figure 2: Pareto optimization showing the relationship between efficiency and power density with optimal LLC stage frequency in a server power supply.

SMPS Package

Infineon is able to offer a comprehensive package portfolio that uses bottom-side cooling (BSC) or top-side cooling (TSC) to meet the requirements of higher density server SMPS, where the SMD package is usually mounted on the PCB using a typical reflow process. The performance of each package type can be compared under the items of components, thermal performance and parasitic electrical effects.

For bottom-side cooling (see Figure 3), heat is directed from the package bottom heat sink (exposed pad) through the PCB to an external heat sink mounted on the opposite side of the board. This means that when using an FR4-based board, thermal vias (through the PCB below) are required for heat transfer. On the bottom of the board, the external heat sink is mounted in the area above the thermal vias. The heat sink and PCB are electrically isolated using a thermal interface material (TIM). In order to reduce the system thermal impedance, foil with good thermal admittance and a thickness in the range of 100 to 500μm is usually used as the thermal interface material to reduce the transient thermal resistance (Zthja) from junction to ambient.

Figure 3: Schematic diagram of an SMD device using bottom-side cooling (BSC).

However, bottom-side cooling is limited in two ways. First, the thickness of the PCB is determined by the number of copper layers required for the board design and the thermal via density limit. As a result, the effective cross-sectional area for heat transfer through the PCB is reduced relative to the size of the heat sink. Second, the thermal admittance of the thermal interface material is much lower than that of the device heat sink and the external heat sink, so it cannot dissipate as much heat. In some cases, replacing the FR4-based substrate with an insulated metal substrate (IMS) can achieve better heat flow without exceeding the maximum operating temperature of the device or the PCB temperature. For a single-layer IMS PCB design, neither thermal vias nor additional TIMs are required, and the external heat sink can be eliminated by using the aluminum core of the PCB as a heat sink. However, while this reduces Zthja, it reduces the number of temperature cycles on the PCB board (TCoB), especially for leadless SMD packages such as TO-leadless (TOLL) or ThinPAK. This is because IMS-based PCBs are less flexible than FR4-based PCBs.

For the TSC package (see Figure 4), the device heatsink is located on the top of the package and is directly connected to the external heatsink through the TIM (see Figure 4). Here, no heat is passed through the PCB and thermal vias, which means they do not contribute to the total thermal resistance. This improves the overall thermal conductivity and allows for higher maximum power dissipation of the package. Another advantage of the TSC is that it frees up space on the opposite side of the PCB for other devices such as gate drivers or passive components. This space can also be used to layout signal links under the package body.

Figure 4: Schematic diagram of an SMD device using top-side cooling (TSC).

To provide a good thermal interface, it is recommended that a certain degree of force be applied when attaching the heat sink to the TSC device. For SMD packages with positive stand-off leads (Figure 5), this force, as well as forces caused by other temperature cycles, are absorbed by the package leads, allowing the QDPAK device to undergo a large number of TCoB cycles. However, for negative stand-off packages, system reliability issues that can increase design and manufacturing complexity must be avoided. In addition, negative stand-off packages have the advantage of lower Zthja due to reduced package height tolerances (which allows the use of thinner thermal interface materials). However, when other tolerances such as PCB warpage are taken into account, especially for larger PCBs with multiple power devices using standard heat sinks, the negative stand-off package advantage becomes less important.

Figure 5: Positive package standoff height (left) and negative package standoff height (right).

Figure 6 shows a schematic diagram of a common heat sink layout method, where a TIM (consisting of insulating foil and gap filler) is stacked between the device and the heat sink, where the gap filler is used to compensate for manufacturing tolerances. This heat transfer method must ensure reliable electrical insulation between the device and the external heat sink. In addition, the gap filler material must meet the necessary breakdown level requirements, and it is also important to prevent the gap filler from pores or particles from being enclosed during the PCB assembly process. A clean manufacturing environment helps reduce contaminants introduced during the system assembly process and reduces the risk of system failure caused by this.

Figure 6: Electrically isolating foil and gap filler between external heat sink and device.

To further reduce Zthja and dynamic power dissipation through the TSC, it is recommended to use an intermediate heat sink soldered directly to the package heat sink (see Figure 7). The thermal capacity of this additional heat sink can store more heat (for up to a few seconds) and then transfer it further to the standard heat sink and the external environment. To achieve even lower Zthja, the standard heat sink and TIM can be removed, with a heat spreader as the main heat sink and direct cooling with fan-forced airflow possible.

Figure 7: Single device vapor chamber installation.

Thermal performance

Figure 8 shows the time variation of Zthja for various THD, BSC SMD and TSC SMD packages mounted on a FR4 based PCB with forced air cooling. All packages contain the same device type internally and are assumed to have the same power dissipation. It can be seen that the Zthja of the DDPAK (TSC package) is 60% lower than the TO263 (BSC package) despite the same effective cooling area for both packages. This is because the DDPAK avoids the requirement of using the “thermal vias” discussed previously. The graph shows that top side cooled packages can achieve Zthja values ​​comparable to through hole devices (THD) and it can also be seen that using a thin layer of isolation material with an equivalently high thermal admittance (λ) is key to achieving good Zthja. Furthermore, the use of gap fillers and isolation foils (λ even higher) allows the TSC package to provide Zthja values ​​even lower than THD.

Figure 8: Typical transient thermal resistance junction-to-ambient values ​​for various packages with forced convection cooling. (Zthja)

Low inductance packaging advantage in high frequency operation

Figure 9 shows the effect of increasing the package source inductance (LSc) from 0 to 4 nH on the turn-on transient. The increase in drain current (di/dt) causes the induced voltage across LSc to drop. This effect reduces the gate drive voltage and gate current, which means that the voltage transient takes longer and the losses increase. The same mechanism applies in reverse to the turn-off transient.

Figure 9: Effect of package source inductance on switching (left) and resulting losses (right).

The negative impact of LSc can be eliminated by using a separate source sense pin (Kelvin source) to reduce switching losses (see Figure 10). Using a source sense connection to drive the gate of the switching device, LSc can be placed outside the gate drive loop. Therefore, the sensed voltage peak is not fed back to the drive circuit, unlike the standard configuration using a single source connection. However, it is important to note that although the Kelvin source package solves the negative impact of LSc on gate drive and switching speed, it still increases the total loop inductance, which is a very critical parameter that can cause ringing in fast switching applications, such as server SMPS using wide bandgap (WBG) switching devices. Therefore, even when using a Kelvin source, LSc should be minimized.