Cadence Achieves PCIe 5.0 PHY and Controller IP Compliance Certification for TSMC Advanced Processes

Cadence Achieves PCIe 5.0 PHY and Controller IP Compliance Certification for TSMC Advanced Processes

Shanghai, China, June 23, 2022 - Cadence Design Systems, Inc. (Cadence) today announced that its PHY and controller IP for the PCI Express® (PCIe®) 5.0 specification for TSMC N7, N6 and N5 process technologies passed PCI-SIG® certification testing at the industry's first PCIe 5.0 specification compliance certification event held in April. The Cadence® solution has been fully tested and meets the full 32GT/s speed requirements of PCIe 5.0 technology. The compliance program provides designers with test procedures to evaluate whether the PCIe 5.0 interface of the system-on-chip (SoC) design will operate as expected.

Cadence IP for PCIe 5.0 technology includes PHY, supporting controllers and verification IP (VIP), which are mainly used for system-level chip design for high-bandwidth hyperscale computing, networking and storage applications. Using Cadence PHY and controller subsystems for PCIe 5.0 architecture , customers can design system-level chips with extremely low power consumption and accelerate time to market.

“We are pleased to see Cadence achieve PCIe 5.0 protocol compliance across its full portfolio of IP for TSMC’s advanced processes,” said Suk Lee, vice president of Design Infrastructure Management at TSMC. “Our continued close collaboration with Cadence will help our mutual customers meet stringent power and performance requirements and accelerate silicon innovation with leading-edge design solutions based on TSMC’s advanced technologies.”

“With customer-proven lowest power consumption, Cadence PHY and controller IP compliant with the PCIe 5.0 specification enables customers to develop extremely energy-efficient SoCs,” said Sanjive Agarwala, vice president and general manager of IP at Cadence. “With our multi-channel on-chip subsystem solutions, our customers can see IP compliance in a form factor that matches their target applications.”

“The Cadence PHY and controller test chips for the PCIe 5.0 specification performed well in compliance testing on the Xgig Exerciser and Analyzer platform, consistent with previous test results,” said Tom Fawcett, senior vice president and general manager of the Lab and Products Business Unit at VIAVI Solutions. “Cadence is a leader in high-bandwidth, hyperscale SoC IP, and their successful track record in PCI-SIG compliance activities demonstrates their continued confidence in their solutions and technology as a whole.”

“Intel is committed to industry-wide innovation and rigorous compatibility testing through the open PCI Express standard,” said Jim Pappas, director of technical programs at Intel Corporation. “Cadence’s latest PHY and controller IP demonstrates their commitment to PCIe 5.0 performance and interoperability with our 12th Gen Intel Core and 4th Gen Intel Xeon Scalable platforms.”

"As a long-time member of PCI-SIG, Cadence has made significant contributions to the development of PCIe technology," said Al Yanes, chairman of PCI-SIG. "Cadence's active participation in this compliance program is helping to drive the continued adoption of the PCIe architecture."

Cadence IP for PCIe 5.0 architecture supports Cadence's Intelligent System Design™ strategy to enable superior advanced-node SoC designs. PCIe 5.0 design kits for TSMC N7, N6 and N5 process technologies are now available for licensing and delivery. Cadence's full range of design IP solutions for TSMC's advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions.