The secrets behind the design of the first K-band DAC

This article will reveal the design secrets behind the world's first K-band data converter, the EV12DS460A, and introduce the ultra-high-speed process introduced to improve performance and circumvent CMOS design limitations. It will also explain how the compact single-core data converter core combined with carefully considered design has led to a breakthrough performance improvement in the EV12DS460A. Finally, you can see that the subtle differences in wiring and circuit simplification are important factors to consider when designing.

Overview

Microwave system designers are always looking for higher performance and higher operating bandwidth. Simplifying the design and reducing power consumption, size and weight are also issues to consider. UWB data converters can greatly simplify the design of multi-channel transmission systems. Over the years, countless devices have been developed using these features. However, none of them has the performance of the latest digital-to-analog converter (DAC) EV12DS460. In fact, the bandwidth of this new DAC can span a huge spectrum range up to 26.5GHz in the microwave K band.

Some initial thoughts on a monolithic microwave IC (MMIC) emerged at last year's European Microwave IC Conference. Early technical information indicated that such a product could achieve X-band (8 to 12 GHz) performance. Subsequently, detailed broadband testing showed that the performance of this DAC is far more than that. The device can operate in 8 Nyquist zones with a very low noise floor and very few spurious signals.

This device provides a glimpse into the possibility of a future where software-defined microwave systems (SDeMS) become a reality. But to achieve this goal, there are two important questions to answer:

What technology is used to achieve such high performance?

How did the test results of this DAC go?

This article will show how powerful conversion capabilities can be achieved by circumventing the design limitations of CMOS and introducing new ultra-high-speed processes, and how breakthrough performance can be achieved using compact single-core digitizers combined with carefully considered circuit design. You will see that the nuances of routing and circuit simplification are important factors to consider when designing. First, let's look at the high-level architectural choices.

High-level design

The two factors that determine performance are:

Basic architecture

· Speed ​​of processing technology

Most high-speed DACs use time-interleaved multiple cores to increase the sampling rate. However, this approach encounters problems when restoring the output signal, and it is difficult to avoid signal spurs and the resulting performance degradation. We did not use the interleaved DAC approach because its SFDR performance is very poor. We designed this DAC using a split architecture.

Split design

The basic DAC design can be simply understood as a series of binary weighted current sources connected to a summing amplifier. Each "power of 2" element is enabled or not depending on the associated bit position. The advantage of this design is that it is simple to implement and requires only a limited number of elements (1 per bit). In practice, it is very difficult to linearly amplify sources beyond 8 bits.

Architecturally, there is a simple approach to achieve a single core design. By using a hybrid split design (see Figure 1), the discrete DAC divides the conversion task into an m-bit encoding unit and a 2-level (nm) bit binary weight unit to handle LSB accuracy. The encoding process requires some time delay, after which the outputs of the two units are combined into the final multi-bit conversion result.

                                Figure 1: EV12DS460A hybrid split-DAC architecture

As mentioned above, it is very difficult to achieve linearity beyond 8 bits, but by splitting the conversion of multiple bits into MSB and LSB units, the complexity of the core can be greatly reduced. Through careful design, the encoding unit and the binary weight unit can be built from the same switch, resistor and current source.

Simple single core design

The starting point for any converter design is to ensure good static accuracy. In a hybrid splitter design, the accuracy is determined by the error of the binary-weighted LSB unit.

The design goal is to improve SFDR and avoid calibration to achieve better than 0.5LSB performance. The following three data converter configurations need to be considered:

1. 2-bit encoder (3 segments) plus 10-bit weight segment = 13 segments

2. 3-bit encoder (7 segments) plus 9-bit weighted segments = 16 segments

3. 4-bit encoder (15 segments) plus 8-bit weight segments = 23 segments

Initial analysis shows that configuration 1 is the best choice; it has the fewest segments and therefore the smallest core area. However, it has poor static accuracy. To understand this, consider that a 12-bit quantizer can output a full 1V peak-to-peak, which means that the LSB quantization voltage is 244 µV (1Vp-p/4096). Simulations show that the matching for a 9-bit weight segment is 125 µV. This is twice as good as the 12-bit 0.5LSB performance, ensuring the monolithic DAC works. However, because the weight option is 10 bits, there is no way to improve the matching performance further, and 125 µV is the physical limit, so option 1 is not desirable. Simulations also show that option 3 is not desirable because it places too much dynamic load on the clock buffer.

Processing Technology

The design that circumvents the limitations of the CMOS process makes the switching path easier to implement. This approach uses the Infineon heterojunction silicon germanium carbon bipolar process to achieve high raw speed. By introducing the carbon element inherent in the NPN bipolar transistor, the B7HF200 process allows for an extremely thin, highly doped base. High switching speed (200GHz Ft) and low impedance base are the two most important factors for achieving high performance of the DAC.

This process has been used for more than 10 years in high-speed and millimeter-wave applications for a variety of solid-state microwave devices.

                                    Figure 2: Comparison of B7HF200 transistor types

The B7HF200 can be further accelerated by using four layers of copper, which is suitable for low-current density connections. Copper helps reduce parasitic currents, which are a nightmare for high-speed designs.

The Secret of DAC Design

The EV12DS460A's superior performance didn't come about by accident. The architecture has evolved over several generations since the slower 12-bit products introduced in 2011. Even in the early days, performance was excellent, with bandwidths up to 1.5GHz.

The design process focuses on 3 general design principles:

Drive dynamic load of quantizer and reduce line length

Ensure job stability

Output pulse shaping to reduce distortion and improve performance

Dynamic load driving the quantizer

The design of the quantizer is partially reusable (Figure 3). On the right is the quantizer containing 16 segments, while on the left is the analog circuit of the sampling clock system. Putting them together, the bridge connecting the two circuits is Lp and Cp generated by the chip wiring.

                                    Figure 3: Simplified EV12DS460A input driver

To support sampling rates of 6 to 7Gsp, the clock source must have low jitter and short transient times. At 6Gsps, the clock period is only 166ps. Ensuring clean, fast transients is critical to ensuring fast quantization and sampling. However, in this design, the relatively high quantizer full-scale current is set to 20mA. To drive this fast, a complex driver is required, including differential pairs and output circuits with very low output impedance.

For this driver circuit, the output impedance Zout can be expressed as:

Zout = (1/gm + Rbb + Rg)/Beta(f), where gm is the transistor transconductance (1/gm=1,25 ohms), Rbb is the output impedance, Rg is the output impedance of the differential pair and Beta(f) is the dynamic current gain of the transistor as a function of frequency.

Considering the specifications of the B7HF200 process (cut-off frequency fT = 200 GHz), the current gain Beta(f) at 20 GHz is equal to 10. At the same time, the intrinsic base impedance of the extremely low bipolar transistor makes Rbb 25 ohms.

Rg should also be as small as possible, but not too small to avoid increasing the bias current too much, resulting in increased power consumption. About 50 ohms is a suitable value.

Finally, a rough estimate of the output impedance is: Zout = (1.25 + 25+ 50)/10 = ~ 7.5 ohms. Low output impedance is key to fast operation of the device.

To maintain a 300mV pulse amplitude at the output buffer, 300mV is required to drive the 50 ohm termination (300mV/50 = 6mA). Further optimization of Rg will slightly improve the impedance, but at the expense of higher power dissipation. Cutting Rg in half increases the bias current to 12mA.

Reduce line length to ensure DAC stability

The importance of line length and its effect on parasitics in high-speed designs is discussed below. Each quantizer segment in the above design is only 50 µm wide, so the total signal line length for 16 segments is 800 µm (16 x 50 µm). Reducing line length is very useful.

The global time constant of EV12DS460A is related to the following three factors:

1. Dynamic load capacitance (CL) is about 0.5 pF (CL=gm.Tf with gm = ΔI/ΔV = ~ 20mA/25mV .Tf transistor forward transition time = 0.8 ps)

2. The passive parasitic capacitance (CP) of the metal signal line is about 0.5 pF

3. The passive parasitic inductance (LP) of the metal signal line is about 50 pH

Under the worst-case conditions, the global time constant ΣT can be calculated as follows:

ΣT = Salt.CL + Salt.CP + LP/Salt, so ΣT = 7.5Ω. 0.5pF + 7.5 Ω.500fF + 50pH/7.5 Ω = 3.75 ps + 3.75 ps + 6.66 ps = ~14 ps

This time constant is related to the 35ps rise and fall time (tr/tf) of the DAC data. Furthermore, at this level, tr/tf represent less than 20% of the entire clock period (166ps), which produces fast enough clock edges to support a preliminary bandwidth estimate of 10GHz, meeting the design goal of the DAC.

Beyond the initial estimates, we used some special techniques to ensure the dynamic stability of the DAC. We achieved performance with maximum overshoot (+4%) and minimum rebound (-2%). The B7HF200 process provides low-impedance copper plating technology to help further adjust and improve key nodes of the chip. The resulting excellent performance (clean 6GHz sampling) is shown in the form of a step response in Figure 4.

                             Figure 4: Step response with 30ps rise time after loading

Improve dynamic performance through output pulse shaping

Four output pulse shaping modes (NRZ, NRTZ, RTZ, RF) are provided to help system designers tailor the DAC's dynamic response performance to a specific output frequency band, making the design more convenient. Most quantizer distortion is related to switching transients. Any switching glitches will be superimposed on the final output signal (Figure 5). If these glitches can be removed, the output spectral purity will be greatly improved.

                  Figure 5: Conceptual diagram of DAC pulse shaping and expanded waveforms for NRTZ and RF modes

To achieve the pulse shaping described above, we force the DAC output to 0 before the edge of each transient segment. The output waveform can be seen in the NRTZ and RF mode figures. Pulse shaping is controlled via a 3-wire serial interface, which has two user-controllable parameters: Shaped Pulse Width (RPW) and Shaped Pulse Center (RPB). If all glitches are removed, the pulse center must coincide with the center of the transient edge. Note that this technique sacrifices a small amount of output signal strength (relative to the area defined by RPW).

特性曲线（图6）表明脉冲整形带来的优势。这些数据展示了两种RPW设置（如果您对信号偏置不了解，请阅读这里）时横跨8个奈奎斯特区间的高达27GHz (采样率fs = 6 & 7Gsps)的频谱。注意采样率的提高显著地扩展了典型的SINC (sin(x)/x) DAC 输出特性曲线。

          Figure 6: Output power spectrum of the DAC EV12DS460 in two pulse shaping modes (sampling rate 6/7Gsps)

Due to waveform shaping (H3 from -57dBm to -69dBm), the performance of the third harmonic is improved by +12dB, which greatly improves the performance of the DAC. For comparison, we generate the following spectrum with waveform shaping (NRTZ mode) and without waveform shaping (NRZ mode) at 6Gsps sampling rate and Fout = 2940MHz (Figure 7). In NRTZ mode, the performance improvement brought by waveform shaping is very obvious.

          Figure 7: Single tone spectrum at 6 GSps, Fout = 2940MHz, with and without wave shaping

Measured Performance

The output 3dB bandwidth is 7GHz maximum and the sampling rate of 6Gsps guarantees an instantaneous bandwidth of 3GHz. The useful output power is very obvious in the X-band (Figure 8a). The curve shows a single-tone carrier at 11950MHz in the fourth Nyquist zone with an SFDR of 50dBc. Here the 4th harmonic dominates the SFDR. This carrier spectrum was carefully selected to make the harmonic signals easier to observe at the edge of the X-band because they appear in a natural harmonic order.

If the carrier frequency is increased to K-band (Figure 8), the signal reference is set to 23950MHz in the 8th Nyquist interval, and the 2nd harmonic dominates the SFDR (-36.5dBc). Obviously, the purity of the harmonics has been significantly improved.

                              Figure 8: SFDR at 11950 MHz and 23950 MHz

These plots also contain other outstanding performance indicators. Each plot shows non-harmonic spurs at the mid-frequency point. These spurs are related to the incomplete mixed signal rejection of the DAC 4:1 input multiplexer. These spurs peak at -80dBm, which is quite good. The noise floor of the DAC is close to about -110dBm.

It is not difficult to test data converters in the lab using single-tone or multi-tone signals. The results of these tests do not fully indicate the performance of the DAC. Today's data communication systems deploy complex modules over large bandwidths, so more effective wideband testing methods are needed. This is where the noise power ratio (NPR) is very useful. It tests the DAC over a wide bandwidth and can show how the signal contains multiple incoherent narrowband frequencies and how they affect and interfere with each other when mixed by the DAC. Obviously, a DAC with an NPR indicator close to that of an ideal n-bit device is a very good wideband device.

NPR testing is usually done by a digital spectrum of Gaussian noise power density. Applying a (digital) notch filter to this digital spectrum in the frequency domain will yield a "quiet" region within the bandwidth of interest. This digital spectrum is then sent to the DAC, and the NPR value is calculated by averaging the power density ratio inside and outside the notch. For an ideal DAC, the signal power inside the notch is only related to the quantization noise. For a real DAC, the quantization noise is related to the noise caused by thermal noise, clock jitter, and inter-channel intermodulation.

The wideband NPR of this device is shown in the figure below (Figure 9). The sampling rate of 7Gsps results in a synthetic bandwidth of 3.150GHz. The NPR is 42.6dB, and the equivalent effective number of bits (ENOB) is 8.6. Note that the flatness of the NPR is quite good all the way to 3325MHz.

                          Figure 9: Wideband NPR with 30MHz notch at 3.15 GHz bandwidth

The second NPR characteristic in Figure 10 replicates the 3.150/2.700 GHz NPR spectrum over a 22 GHz range. The DAC is sampling at 7/6 GSps and operating in RF mode. These plots illustrate one of the benefits of increasing the sampling rate. It not only affects the maximum instantaneous bandwidth produced by the DAC, but also extends the SINC characteristic and output power in the high Nyquist interval.

      Figure 10: Repeated NPR spectra of multiple Nyquist intervals – K-band NPR is significantly improved at 7Gsps

Other cutting-edge DACs

Texas Instruments recently released a 14-bit 8.9Gsps RF DAC that uses a 40nm CMOS process and supports 4G LTE applications. Its SFDR is 50dBc at 8.9Gsps (Fout = 4300MHz) [3]. Although this DAC can support a sampling rate of 8.9Gsps, there is no test data exceeding 4300MHz, while most microwave frequency bands exceed 4300MHz.

Analog Devices is also developing an 11/16-bit, 12Gsps DAC (AD9161/AD9162) that can sample at 12Gsps in RF mode (also called hybrid mode). In RF mode, because the data is reversed every half clock cycle, it seems that the DAC is sampling at 12Gsps. For the EV12DS460A in RF mode (Figure 5), data reversal is not taken into account in the nominal sampling rate (6Gsps). Therefore, the sampling rate of the EV12DS460A and AD9161/62 is the same. This can also be proved by the 3GHz instantaneous bandwidth.

The best SFDR of the Analog Devices device in the first two Nyquist zones is 65dBc (Fclock = 5Gsps, Fout = 4000MHz). However, its performance drops sharply above 7500MHz. The output power is only -66dBm at Fout = 7500MHz, so it does not work well in the X-band and K-band.

Conclusion

The release of the EV12DS460 brings microwave engineers a wideband DAC with bandwidth from DC to K-band frequencies. Although this device is not the only DAC with Gsps sampling rate, as mentioned above, it is the first DAC with a synthetic bandwidth spanning multiple Nyquist zones while maintaining excellent spectral purity. It opens up an exciting new field for new millimeter-wave applications.