FPGA Implementation of Wideband Spectrum Sensing Technology in Cognitive Radio

Project Name: FPGA Implementation of Wideband Spectrum Sensing Technology in Cognitive Radio

Project background: With the rapid development of wireless communication technology, the number of wireless users has increased dramatically, and available spectrum resources have become increasingly scarce. At present, most spectrum resources adopt a fixed allocation mode, and a special frequency management department allocates specific authorized frequency bands for different communication services. As for communication services working in unlicensed frequency bands, due to the rapid development in recent years, unlicensed frequency bands are becoming increasingly saturated. Cognitive radio technology solves the above contradictions. It can automatically detect the surrounding environment, intelligently adjust its own parameters, detect spectrum holes and use idle frequency bands for communication without interfering with the authorized frequency band. In the past, spectrum detection was mostly based on narrowband detection, rarely detecting broadband spectrum, and not considering the impact of noise uncertainty on energy detection. Narrowband detection can only detect one channel at a time, which greatly weakens the efficiency of spectrum perception and is not conducive to improving spectrum utilization. For example, at a certain moment, it is detected that a certain channel is in use, and CR users cannot use this channel, but there are still a large number of idle channels. Since only one channel can be detected at a time, CR users cannot use this channel. The broadband spectrum detection proposed in this project can detect multiple channels at a time, which solves the limitations of previous narrowband spectrum detection and solves the problem. Energy detection is simple and easy to implement and can achieve blind perception and is widely used. The decision threshold of energy detection depends on the power of environmental noise. Ideal energy detection often assumes that the noise power is known, but in actual environments, the noise power is time-varying, that is, the noise has uncertainty, which leads to a decrease in energy detection performance. In this project, we will design an algorithm module to overcome noise uncertainty and implement it with FPGA.

Project Description:

This project mainly studies the FPGA implementation of cognitive radio broadband spectrum sensing technology, using the most commonly used detection method in cognitive radio - energy detection. First, the input signal is anti-aliased filtered, and then A/D sampling is performed to obtain a set of digital signals, and then a 64-point high-speed parallel pipeline FFT operation is performed, and the output amplitude-frequency signal is further squared to obtain the power of the signal in each frequency band, and then the 16 historical power data are averaged, and finally the noise uncertainty algorithm is executed to compensate for the noise variance change, so as to judge the utilization of the frequency band and select the spectrum hole for communication.

Project goal: This project aims to design and implement a practical broadband spectrum sensing platform that can achieve broadband spectrum sensing and overcome noise uncertainty.

Project Difficulty: How to design a highly optimized parallel pipeline 64-point FFT algorithm and a high-speed, low-latency sorting algorithm is the key to the design.

Significance of project development: The FPGA implementation of cognitive radio wideband spectrum detection technology overcomes the impact of noise uncertainty on energy detection, solves the previous problems of low narrowband detection efficiency and poor wideband detection performance, and makes wideband spectrum detection technology truly practical.

Development Platform: Spartan-6

Project system solution

According to the project content, our design project plan mainly includes:

Overall project framework

Energy detection module

Energy Detection Algorithm

Energy detection FFT design module

1) Highly optimized complex multiplier design

2) Four-Butterfly-Based Unit Design

3) Pipeline implementation of 16-point FFT

Overcoming noise uncertainty algorithm module

FCME algorithm

Sorting algorithm module implementation

Comparison module implementation

The following is a detailed description of the specific design of each module of the project

(I) Overall framework of the project

The project has two core modules: energy detection module and noise uncertainty overcoming module. The system master is responsible for the timing control of each module.

(II) Energy detection module

Energy Detection Algorithm

Energy detection principle: The starting point of energy detection is that the energy of the signal plus noise is greater than the energy of the noise. First, set a threshold, and then accumulate energy within a certain frequency band. If the accumulated energy is higher than the threshold, it means that there is a signal. If it is lower than the threshold, it means that there is only noise. The energy detection statistic Y can be obtained by directly sampling the time domain signal and then accumulating the squares (it can also be obtained by converting it to the frequency domain using FFT and then squaring the frequency domain signal). The following figure is the energy detection block diagram:

First, the input signal is subjected to anti-aliasing filtering, and then A/D sampling is performed to obtain a set of digital signals. Then, a 64-point high-speed parallel pipeline FFT operation is performed, and then the square is taken to obtain the detection statistic Y, that is, the total energy on the corresponding frequency band, and compared with the set threshold value to determine the spectrum utilization. Previous spectrum detection was based on narrowband detection (narrowband means that the bandwidth of the measured frequency band is small), which can only detect one channel at a time and has low detection efficiency. In this project, we want to achieve broadband detection, which can detect multiple channels at a time, improve detection performance, and effectively overcome the influence of noise uncertainty.

Assuming that a signal transmission requires 2M bandwidth, 32 channels require 64M bandwidth. According to the sampling theorem, the A/D sampling frequency should be at least 128M. This requires that the 64-point FFT operation we designed should be completed within 0.5μs. In order to meet the high-speed performance, we use a parallel pipeline FFT design, which can achieve a higher clock frequency and better meet the requirements of real-time processing.

Energy detection FFT design module

FFT cores are already included in FPGAs, but they are not very efficient. In order to meet the requirements of real-time processing, we designed a highly parallel, pure pipeline 64-point radix-4 FFT.

From the above figure, we can see that we can use 16-point FFT for 64-point FFT, and 16-point FFT uses radix-quad butterfly to complete the operation. The core operations of radix-quad butterfly operation unit are addition and complex multiplication. For addition operation, we use carry-lookahead addition, which has a faster operation speed. Next, we discuss the design of highly optimized complex multiplier.

2.1 Highly Optimized Complex Multiplier Design

Formula for complex multiplication

The following figure is a block diagram of the parallel implementation of a complex multiplier: The multiplier is designed for its own 8-bit input and 16-bit output. In the figure, A+aj and B+bj are the two designed inputs,  is the real part of the output, and  is the imaginary part of the output. A total of two stages of pipelines are required.

Figure 4 Complex multiplier

Since the parallel pipeline FFT design requires a large number of slices, in order to minimize the hardware overhead while ensuring that the clock frequency meets the requirements, we have optimized the twiddle factors in the complex multiplier.

In actual operation, we found that we can make corresponding deformation and derivation processing on the formula of complex multiplication, which can save the number of multipliers. We know that multipliers occupy a large hardware area, and when the number of FFT points is large, more resources will be saved. When the number of FFT points is determined, the rotation factor can be deformed accordingly according to its periodicity, symmetry and Euler formula, reducing the number of multipliers required for calculation and saving a lot of hardware resources. 2.2 Design of base four butterfly unit

According to the principle of radix-4 FFT operation, we can get: x(n) is a finite length sequence of length M. The N-point discrete Fourier transform of x(n) is defined as

make:  ; 

;

;

;

but:

make

,Right now

Figure 5 Basic signal flow diagram of base 4 FFT

2.3 Pipeline Implementation of 16-Point FFT

16-point FFT is an important part of 64-point FFT. The following is a pipeline implementation diagram of 16-point FFT. In order to minimize the hardware overhead while meeting the system clock frequency requirements, we use the rotation factor

The periodicity and symmetry of the 16-point FFT are used to optimize the multipliers and rotation factors, saving more slices.

Figure 6: Pipeline implementation of 16-point FFT

Sorting algorithm module implementation

The sorting algorithm is the core part of the FCME algorithm, and high-speed and efficient sorting is the key technology for the execution of the FCME algorithm. Here we propose an improved sorting scheme to improve the speed of the sorting system. Because the system framework we designed is implemented in a pipeline manner, in order to increase the clock speed, we adopt a new scheme that can effectively improve the speed performance and make the average time algorithm complexity of sorting O(N). It takes n clock cycles to arrange n data, which is more effective than traditional sorting algorithms and has a simple structure and is easy to implement.

The schematic diagram of the parallel sorting mechanism is shown in the figure below. The entire processing unit can use N clock cycles to arrange N data. The D flip-flop is used to perform the necessary data storage and transmission in the N cycles. The N-level cascaded sub-modules include comparators, NAND gates, D flip-flops, and multiplexers. Where n represents the nth sub-module, n = 1, ..N, input data, enable signal. The input data is serial, and the entire sorting algorithm is as follows:

First, all D flip-flops are initialized to the minimum value. The input data is compared with the output data of the D flip-flops in the queue submodule to determine whether to enable the D flip-flops of the corresponding submodule. The multiplexer selects the submodule to which the data is inserted. At the same time, the data in the following submodules are moved to the next submodule in turn, and the data in the previous submodule remains unchanged. Repeat n times to insert all n data into it, thus obtaining an orderly queue.

Comparison module implementation

Based on formula (3), we can see that the implementation of the FCME algorithm also requires a comparison circuit to compare Q(K+1) with the sum of the first k items Q(i). The designed comparison module is as follows:

The control circuit provides an initial value control FIFO to read the energy values ​​of k channels, and then sums the energy through an adder circuit, and compares the energy sum of the first k channels with the energy of the k+1th channel through a comparator. If the former is greater than the latter, it means that the k+1th channel is an idle channel, otherwise the control circuit continues to add 1 to the k value and continue the comparison.

Project Summary

In cognitive radio networks, the essence of spectrum detection is for cognitive users to determine whether there are authorized users in a channel, so as to find available spectrum holes. At the same time, cognitive users need to determine the reappearance of authorized users through spectrum detection and avoid them to avoid or reduce interference to authorized users. The FPGA implementation of broadband spectrum sensing will solve the problem of low detection efficiency of narrowband detection, overcome the impact of noise uncertainty on detection performance, and make broadband spectrum detection technology practical.