Interpretation of ENC28J60 embedded network interface circuit

　　The Ethernet interface implementation scheme based on ENC28J60 is designed, and the design method of the hardware architecture of the system is described. On the basis of briefly introducing the structure, function and peripheral circuit of Ethernet controller ENC28J60, the SPI communication between ENC28J60  and Atmega16  is explained. This scheme is not only low-cost, but also can achieve a transmission rate of more than 500Kbps, meeting the Internet control requirements of embedded systems.

　　Application of ENC28J60  in Embedded Network Interface

　　ENC28J60 can be used to form network terminal nodes with different functions, such as network servers, devices with Internet functions, remote monitoring (data acquisition, diagnosis) equipment, etc. Figure 2 shows the hardware circuit schematic diagram of the embedded network interface based on ENC28J60. The circuit has: 2 LED status indicators are mainly used to display the network connection status, including whether PHY conflicts, whether the connection is established, whether data is received, connection speed, duplex mode, etc.; required bias resistor R3 (2kΩ, accuracy is 1%); high-speed LAN electromagnetic isolation module (i.e. RJ45 Ethernet interface). In the application, the physical port of ENC28J60  must be connected to the isolation transformer HR901170A in accordance with the requirements of IEEE802.3 for the physical layer specification, such as the spacing between the RJ45  jack and the isolation transformer should be as small as possible, and the routing of the output and input differential signal pairs should be well isolated.

　　The main controller in the circuit uses Atmel's ATmega16 microcontroller, which has an advanced RISC (Reduced Instruction Set Computer) structure, 16 kB programmable Flash memory, 512 B EEPROM and 1 kB on-chip SRAM, and has a wealth of peripheral interfaces. Its SPI interface allows ATmega16 to perform high-speed synchronous data transmission with peripherals. In this design, ATmega16 SPI is configured as a master mode, and ENC28J60 is a slave device. The SPI working mode of ATmega16 is set by CPOL and CPHA. According to the SPI read and write timing of ENC28J60, the SPI working mode of ATmega16 should be set to mode 0. ATmega16 achieves synchronization with ENC28J60 by setting the CS pin of ENC28J60 low. The SPI clock is started by the data written to the SPI transmit buffer register. The data transmission order on the SPI MOSI (PB5) pin is controlled by the DORD bit of the register SPCR. When set, the LSB (least significant bit) of the data is sent first, otherwise the MSB (most significant bit) of the data is sent first. We choose to send the MSB first, and at the same time, the received data is transferred to the receive buffer register. The CPU reads the received data from the receive buffer by right alignment. It should be noted that when multiple data need to be read from the ENC28J60, even if the ENC28J60  does not need the data serially output by the ATmega16, a data must be written to the SPI transmit buffer before each data is read to start the SPI interface clock. Since the SPI system has only one buffer in the transmit direction and two buffers in the receive direction, it is necessary to wait until the shift process is completed before writing to the SPI data register when sending; and when receiving data, it is necessary to read the currently received data by accessing the SPI  data register before the next byte shift process is completed, otherwise the first data will be lost.