Design of a Unipolar Frequency-doubling Voltage-type SPWM Soft-Switching DC/AC Inverter

　   1 Introduction

　　At present, PWM power conversion technology has been widely used. For PWM inverters working in hard switching state, due to their large switching losses and serious EMI, it is difficult to meet the requirements of high frequency and green switching power supply. In order to overcome the shortcomings of hard switching, soft switching technology has been rapidly developed, especially the DC/DC converter phase shift soft switching technology has become mature. However, for DC/AC converters, due to factors such as the quality of their output waveform, there is currently no real soft switching product. Although some DC/AC converter topologies and soft switching control technologies have appeared [1][2][3], these methods are not yet truly practical.

　　Reference [4] introduces the use of resonant circuits to achieve soft switching, which is a relatively good method. However, this technology requires tracking the voltage and current in the circuit and achieving soft switching at the zero crossing of the voltage and current, which inevitably makes the circuit complicated. In order to better solve this problem, reference [5] introduces non-resonant soft switching PWM technology using inductor commutation. However, this technology is only applicable to bipolar voltage-controlled DC/AC converter circuits. Based on the analysis of reference [5], this paper designs a unipolar frequency-doubled SPWM [6] soft switching DC/AC converter circuit.

　　2 Unipolar frequency doubled SPWM soft switching DC/AC converter main circuit

　　2.1 Main circuit structure

　　Figure 1 shows the main circuit schematic of the new unipolar frequency-doubled SPWM soft-switching DC/AC inverter. Figure 2 shows its main working waveform. This circuit adds capacitors C1, C2, C3, C4, Cr1, Cr2, CE1, CE2 and inductors Lr1, Lr2 on the basis of the hard-switching SPWM DC/AC inverter, where capacitors C1=C2=C3=C4, Cr1=Cr2, inductors Lr1=Lr2, and large-capacity electrolytic capacitors CE1=CE2 are regarded as constant voltage sources. These components create conditions for the four power tubes in the circuit to achieve zero voltage switching (ZVS).

Figure 1 Main circuit structure

Figure 2 Main working waveform of the main circuit

　　2.2 Implementation Principle of Soft Switching

　　The voltage and current directions in the following formulas are based on the reference directions in Figure 1. It is assumed that the load current io is continuous.

　　1) Working mode 1 (t0-t1 time period)

　　During this period, S1 and S3 are turned on, S2 and S4 are turned off, iLr1 flows from the positive electrode of the power supply ED through S1, Cr1, Lr1, CE2, to the negative electrode of ED and gradually increases; at the same time, the capacitor CE1 continues to discharge through S3, Cr2, Lr2, and the discharge current iLr2 continues to rise. At time t1, iLr2 reaches the maximum, that is,

iLr2(ωt1)=αIomsinωt1-(1-α2sin2ωt1)(1)

　　Where: α is the modulation ratio; Iom is the maximum load current, Iom=ED/RL; ω=2πfc, fc is the carrier frequency.

　　The corresponding equivalent circuit topology is shown in Figure 3(a).

　　2) Working mode 2 (time period t1-t2)

　　During this time period, the power tube S1 continues to be turned on, and iLr1 continues to increase. At t1, S3 is turned off, and the collector current i3 is transferred from the switch tube S3 to the buffer capacitor C3 to charge C3. The voltage on C3 starts to rise from zero, and S3 is turned off with zero voltage. At the same time, the energy stored in C4 is discharged through the Cr2, Lr2, and CE2 circuits. Its equivalent circuit topology is shown in Figure 3(b). It can be seen from the figure that the parameters of the C3 charging circuit and the C4 discharging circuit are the same. Therefore, at t=t2, vC3=ED, vC4=0. The charging and discharging time t21 is

t21=t2－t1=（2）

　　3) Working mode 3 (t2-t3 time period)

　　At t=t2, D4 is turned on, providing a path for the circulating current iL2 to continue flowing, and vC4 is clamped to zero, that is, vC4=0. If the trigger signal of S4 arrives before iL2=0, S4 will be turned on at zero voltage. Its equivalent topology is shown in Figure 3(c).

　　4) Working mode 4 (t3-t4 time period)

　　At t3, S4 is turned on with zero voltage. The circulating current iL2 continues to flow through D4 and the flow is completed at t4. The flow time t41 is

t41=t4－t1=－（3）

　　Its equivalent circuit topology is shown in Figure 3(d).

　　5) Working mode 5 (t4-t5 time period)

　　After time t4, the collector current of S4 starts to rise from zero. The power supply ED provides energy to the load. Its equivalent circuit topology is shown in Figure 3(d).

(a) t0－t1

(b) t1－t2

(c) t2－t3

(d) t3－t4

Figure 3 Equivalent circuit topology in various modes

　　At time t5, S1 is turned off, and due to the existence of buffer capacitor C1, S1 is turned off at zero voltage. After time t5, the circuit enters the second half of the switching cycle, and its working mode is the same as above.

　　2.3 Discussion of Circuit Characteristics

　　1) No voltage/current detection device is required in the main circuit to achieve soft switching of the switch tube.

　　2) Since the switch tube realizes soft switching, the output voltage waveform of the inverter will not be distorted due to the existence of dead time td.

　　3) The reverse recovery current of the two diodes in the same bridge arm will not cause the bridge arm to be directly turned on.

　　4) The control circuit adopts a unipolar double-frequency voltage control signal. When the main circuit transitions in each time period in a cycle, only the state of one switch tube changes. This reduces the number of switch actions when a certain number of pulses is generated, or in other words, the number of pulses in the output voltage can be doubled with the same switching frequency. This is beneficial to reducing switching losses and improving the working efficiency of the inverter.

　　5) In the SPWM output voltage waveform of the main circuit, there are only positive voltage pulses in the positive direction and only negative voltage pulses in the negative direction, which is beneficial to reducing the output filtering parameters and improving the output waveform quality.

　　Since the control signal of the leading bridge arm of the unipolar double frequency SPWM soft switching DC/AC converter differs by 180° from the control signal of the lagging bridge arm, the switching action of the leading bridge arm is relatively independent of the lagging arm. This lays a good foundation for further research on the three-phase inverter inductive commutation frequency modulation soft switching technology with a 120° difference in the driving signals on each bridge arm.         3 Main parameter design

　　3.1 Design of inductor Lr1 (Lr2)

　　From the analysis in 2.3, we know

≥td（4）

　　Substituting equation (1) into equation (4) and rearranging it, we have

Lr2≤(1-α)(1+α-4fctd)(5)

　　3.2 Design of capacitor Cr1 (Cr2)

　　From the analysis of the working process in 2.2, it can be seen that when the charging and discharging time of the buffer capacitors C3 and C4 is very short, the equivalent topology of Figure 1 is shown in Figure 4.

Figure 4 Equivalent circuit topology

　　According to the equivalent topology, equation (6) holds true

di3/dt=（ED－vCr2）/Lr2;dvCr2/dt=iLr2/Cr2(6)

　　Further, the maximum value of i3 is

i3max=ED/4fcLr2（1+1/48fc2Lr2Cr2）(7)

　　From formula (7), we can see that in order to transfer energy to the load as much as possible, the collector current i3 should be as large as possible, so the smaller Cr2, the better. However, if Cr2 is too small, the resonant impedance will be too large, and the freewheeling time will be too long, which will affect the drive signal, the duty cycle of the switch will be seriously lost, and the output power will be reduced. In order to take both into account, in practice, 1/48fc2Lr2Cr2≤0.1 is generally taken, so

Cr2≥5/24fc2Lr2（8）

　　3.3 Design of buffer capacitor C1 (C2, C3, C4)

　　When the buffer capacitor C1 is too large, the charge and discharge time constant is long. If the charge and discharge time is greater than the dead time td, the bridge arm shoot-through phenomenon will occur. To ensure that this phenomenon does not occur, the buffer capacitor value cannot be too large.

　　From formula (2), we have

≤td（9）

　　When sinωt=1, iL2 is the smallest and the left side of equation (9) is the largest. Substituting equation (1) into (9), we have

C1≤td（10）

　　4 Experimental waveforms and conclusion

　　According to the above analysis and parameter design, the experiment was carried out with Figure 1 as the main circuit. The specific circuit parameters are: switching frequency f=12.5kHz, 1MBH60D-100 IGBT is selected as the main power tube, modulation ratio α=0.8, buffer capacitor C1=C2=C3=C4=18nF, Cr1=Cr2=16.7μF, Lr1=Lr2=80μH, Lf=1.0mH, Cf=18μF, RL=10Ω. Figures 5-8 are the waveforms obtained in the experiment.

Figure 5 S1 (S2) driving waveform and tube voltage drop waveform

Figure 6 S3 (S4) driving waveform and tube voltage drop waveform

Figure 7 Output voltage waveform of unipolar frequency-doubled hard-switching DC/AC inverter

Figure 8 Output voltage waveform of unipolar frequency-doubled soft-switching DC/AC inverter

　　Figures 5 and 6 show the waveforms of the tube voltage drop and the driving signal of the switching tube in the main circuit (in the figure: 1 - driving signal waveform, 2 - switching tube voltage drop waveform), Figure 7 shows the output voltage waveform of the hard-switching DC/AC converter, and Figure 8 shows the output voltage waveform of the soft-switching DC/AC converter.

　　It can be seen from Figures 5 and 6 that before the driving signal of the switch tube arrives, the voltage drop across the switch tube is zero, and the switch tube achieves zero voltage turn-on; after the driving signal is turned off, the voltage across the switch tube remains at zero, and the switch tube achieves zero voltage turn-off.

　　It can be seen from Figures 7 and 8 that when soft switching is not implemented, the output voltage waveform quality of the main circuit is poor and has large "burrs" (generated when the switch tube is switching). The existence of these "burrs" will cause serious electromagnetic interference (EMI) to the circuit itself and other surrounding circuits and electrical appliances. After adding the soft switching circuit, the output voltage waveform quality has been greatly improved, and there are no "burrs", which better suppresses electromagnetic interference (EMI).