Embedded PCB technology (Part 2)-EEWORLD

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5 Embedded components

When the pad connection method is used, most components that can be embedded using surface mounting technologies such as reflow soldering or adhesives are embedded. In order to avoid an extreme increase in board thickness, components with small component thickness are used. In the case of bare chips or WLP, most of them grind the back side of silicon (Si), and the height after mounting including bumps is less than (300~150) mm. For passive components, low-profile types such as 0603, 0402 or 1005 are used. When the via connection method is used, the various examples of plating connection and conductive adhesive connection introduced above are all components using Cu electrodes. When used as embedded components, the thickness of passive components with copper (Cu) electrodes is 150 mm, which is one of the goals, and there are also examples of developing thinner components.

6EPASD Evaluation Analysis TV (TestVehicle)

6.1 Test Vehicle (TV) Overview

In order to clarify the technical issues of component embedding in PCB, TV (Test Vehicle) in the evaluation and analysis WG was produced and evaluated. Since 2007, the discussion on structure and design has been repeated, and finally the structure of bare chip embedded in substrate as shown in Figure 9 was produced. The circuit layer is 4 layers, and components are embedded between L2 and L3. According to the purpose of component embedding in PCB, the initial comments should be the same as those of HDI substrate, and the issues unique to component embedding are considered to be the most essential issues. Priority is given to the extremely easy manufacturing of the parts other than the embedded part, and the connection between layers is through-hole. It is manufactured using halogen-free FR-4 and FR-5 substrates respectively.

The embedded components are "SIPOSTEG" provided by SIPOS (System Integration Platform Organization Standard), forming a pad configuration like a daisy chain pattern connected to the PCB. Figure 10 shows this pattern and main specifications. Among them, gold (Au) stud bumps are formed on the electrodes, and the face-down flip chip connection installation method is adopted. At this time, two methods, thermocompression bonding and ultrasonic bonding, are used. Therefore, a total of 4 samples with two materials and two installation methods are made.

6.2 Evaluation results

TV production was implemented in 2008, and evaluation and analysis were carried out in 2009. First, in order to evaluate the reflow heat resistance, pre-treatment was carried out using JEDEC Class 3 conditions. Many samples developed blistering after reflow.

In addition, disconnection or resistance increase may occur.

Figure 11 shows an example of cross-sectional analysis. Peeling occurred between the bottom glue resin under the embedded chip and the chip, and some peeling occurred at the interface between the bolt-shaped bump and the PCB electrode. This peeling is the cause of blistering. Heat-resistant FR-5 also had some blisters. Since there was no significant difference among the four conditions. Therefore, it is believed that the main cause of blistering is the structure itself. According to the results of the cross-sectional analysis, the chip itself warped significantly, because the inherent residual stress after embedding was released during reflow soldering and deformed, or due to the size of the chip itself or the influence of the PCB pattern. Regarding warping, when installed on the inner layer board, due to the difference in thermal expansion coefficient between the chip and the inner layer board, it showed convex warping, but it is worth noting that the cross section after blistering is reversed to concave warping as shown in Figure 11.

The evaluation of blistering is essentially caused by the popcorn phenomenon. The same blistering was found in the installation methods using two different primer resins, so it is believed that the PCB structure has a great influence. In order to investigate this phenomenon, TV-1' core material thickness was 0.1 mm and 0.3 mm for the second time, and the conductor pattern had two types: the copper (Cu) intermediate (Beta) pattern used in TV-1 and the mesh (Mesh) pattern of PCB. A total of four samples. Figure 12 shows the conductor pattern and layer structure of TV-1'PCB. Various structures were subjected to 5 reflow soldering heat resistance tests. The core material 0.1mm/Cu intermediate pattern with the same structure as TV-1' reproduced the blistering phenomenon, while other structures did not have blistering or resistance increase, confirming the effect of structural changes.

6.3 Thermal deformation analysis

In order to examine the influence of the thickness of the substrate or the line conductor pattern on the thermal deformation behavior of the components embedded in the PCB, the simulation was used to analyze the experimental results obtained so far. A three-dimensional model (Model) was made based on the Geber data of the EPADS TV described in the previous section, and it was obtained by analyzing the thermal deformation behavior when heated from room temperature to 260°C. ADINA8.6 (manufactured by ADINA, USA) was used for nonlinear elastic analysis during the analysis. The analysis was based on TV-1′ as the standard. The substrate thickness was 0.1 mm and 0.3 mm, and the conductor of the PCB was set to copper (Cu) intermediate pattern and mesh pattern, and a total of four combinations of analysis were implemented. The model made is as follows.

(a) Model 1 core material 0.1 mm thick/mesh pattern.

(b) Model 2 core material 0.1 mm thick/middle pattern.

(d) Model 4 core material 0.3 mm thick/middle pattern.

The embedded chip is 0.1 mm and 10 mm thick. It has the same structure as TV with gold (Au) bumps around the periphery and primer resin filled underneath. The actual manufacturing conditions are different. In the analysis, the stress and deformation at room temperature are set to 0, and the thermal deformation behavior when heated to 260 ° C is calculated. Figure 13 shows an example of the thermal deformation analysis results. PCB L1 in the middle shows that the center of the bare chip embedded part shows a tendency to deform in a convex shape. Its surroundings are affected by the deformation of the bare core embedded part. The deformation behavior varies with the location, which is due to the shape and density of the conductor pattern. Among the four models analyzed. Model 2 is equivalent to the structure where TV-1 blistering occurs.

The thermal deformation obtained by analysis is the largest in Model 2, showing the same tendency as the actual substrate. The deformation of Model 2 is 108 mm, and the deformation of other models ranges from 46 mm to 60 mm.

6.4 Comparison with actual thermal deformation measurements

In order to verify the accuracy of thermal deformation analysis, actual measurement of thermal deformation behavior was carried out. The sample was made into TV-1′, and the structure was equivalent to model 1~model 4 of thermal deformation analysis for the test. The non-contact warpage measurement based on the Shadow Moire method was measured while heating to a maximum of 260°C. Figure 14 shows the warpage distribution diagram at room temperature initial state. Contrary to the analysis results, since the L4 side has a convex warpage, PCB L4 is configured on it. Since this warpage direction corresponds to the chip warpage direction after blistering shown in Figure 11, the chip shows different warpage when embedded and when installed.

By measuring several points while increasing the temperature from the initial state at room temperature to 260 °C, it was confirmed that the warping tendency at the initial state at room temperature was small, that is, the L1 side showed warping behavior, which was consistent with the tendency of the simulation. The L1 displacement was calculated based on the warping amount at the initial state at room temperature, and the comparison results with the simulation results are shown in Table 1. The measured results in the structure with a thickness of 0.1 mm greatly exceeded the deformation amount of the simulation results. In particular, model 2 showed a large peeling, and although the appearance was not confirmed, it is possible that fine interlayer peeling may occur. However, in the structure with a thickness of 0.3 mm, the measured results were consistent with the simulation results, indicating that the prediction of thermal deformation of components embedded in PCB is effective. There is still room for research on the peeling point of the two in the structure with a thickness of 0.1 mm. The thermal deformation behavior can be predicted by elastic analysis, which is useful in industry and is expected to help with component embedding.

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