ESBT Technology in High-End Quasi-Resonant Zero-Voltage Switching Flyback Converter

　　The purpose of the emitter switching study is to find the best balance between switching loss and conduction loss (mainly for high voltage applications). The main structure of the emitter switch includes a high voltage power bipolar transistor and a low voltage power MOSFET transistor that drives the bipolar transistor. The two transistors are connected in series, as shown in Figure 1. This structure requires two power supplies : the first power supply supplies current to the base of the power bipolar transistor, and the second power supply supplies the gate of the power MOSFET. Although the base of the power bipolar transistor does not require a proper drive circuit, it is necessary to apply a proper bias to the base to saturate the power bipolar transistor, so the main conduction loss is the sum of the VCE (sat) loss and the input loss of the power bipolar transistor.

　　If the power supply of the power MOSFET transistor is turned off, the leakage current immediately drops to zero, so that the output current changes the current path to ground through the base of the transistor, and this process continues until all minority carriers have moved out of this area and the bipolar transistor structure automatically turns off. This turn-off feature causes the charge stored in the base to be removed quickly, thus reducing the storage time, and most importantly, this structure is basically free of the tail current characteristic inherent in bipolar transistors. This configuration extends the safety limit of the reverse operating region by improving the ability to resist the breakdown voltage on the secondary side. In fact, because the emitter is an open circuit, there is almost no current blocking under the emitter (current blocking can cause hot spots).

　　The first ESBT (Emitter Switched Bipolar Transistor) products were hybrid structures, with specially customized power bipolar transistors assembled in a specially designed 4-pin package, connected in a hybrid series configuration. Integrating a low voltage power MOSFET transistor in this monolithic circuit structure is a major challenge in the ESBT design, especially integrating the power MOSFET transistor in the emitter area of ​​the bipolar transistor module, which is even more difficult to produce a sandwich structure. Although the entire switch is composed of two transistors connected in series, due to the solution adopted, the silicon area is only related to the size of the bipolar transistor (BJT). As

　　shown in Figure 2, two buried layers are used for the emitter and base regions respectively. In fact, since the emitter of the BJT transistor happens to be in the same area as the drain of the low voltage power MOSFET transistor, the buried layer must be properly selected to achieve the required current capability and gain of the BJT and the required breakdown voltage of the power MOSFET transistor. Therefore, a DMOS structure is diffused on a high resistivity buried layer, covering the highly doped emitter region (N-BL). From the perspective of diffusion and deposition layers, the DMOS structure is very similar to the structure of a standard low-voltage power MOSFET transistor, even if the layout of the DMOS structure matches the emitter geometry of the bipolar transistor. Finally, the base contact is placed on the diffusion layer, and the depth needs to reach the base buried layer (P-BL). It should be pointed out that the P-well region under the base contact together with the integrated DMOS constitutes a redundant lateral parasitic insulated gate bipolar transistor IGBT. In fact, due to the characteristics of the emitter switching configuration (a constant voltage is always applied to the base), this IGBT is always in the on state, thus greatly reducing the current handling performance of the ESBT. In order to prevent this harmful phenomenon, it is necessary to add a deep well with appropriate doping level, size and distance from the DMOS.

　　Quasi-Resonant Flyback Topology and Applications with ESBT

　　After the success in high-end industrial applications, we shifted the focus of ESBT development to low-end applications such as laptop adapters, printer power supplies and LCD TV switch power supplies. One of the most prominent and simplest ways to improve energy efficiency is to operate the flyback converter in QR (quasi-resonant mode). The QR flyback converter is a variable frequency version of the standard flyback converter. There are several advantages to using this topology: The QR method uses the otherwise harmful parasitic leakage capacitance to create a zero voltage condition that minimizes the conduction losses of the switch.

　　Variable frequency operation is inherent in this function. The main advantage is related to conducted EMI. In simple terms, the QR flyback structure works by performing so-called valley switching, i.e., turning on at the lowest voltage during the resonance period after the core is demagnetized. The conduction losses are calculated according to the equation Eon = CV2, where V is the on-state voltage and C is the parasitic capacitance. It is best if the switch turns on at zero voltage. Zero voltage switching is achieved by choosing the flyback voltage equal to the input voltage. However, this configuration will cause a large voltage stress on the chip. For a normal offline converter, this voltage can reach 1200V (if there is no clamping circuit) under normal transformer leakage inductance conditions. Regardless of the rated voltage and current, the ESBT has a low voltage drop and excellent switching performance, so the ESBT is the most cost-effective converter solution.

　　We redesigned a 180W, 19V single output adapter by changing the 600W power MOSFET transistor of the main switch to a 1200V ESBT transistor and removing the clamping network in the original design. The power MOSFET voltage stress is much higher than the rated breakdown voltage, so avalanche and unsafe operating conditions may occur. The 600V breakdown voltage was chosen because of the need for extremely low RDS(on) (high energy efficiency). To prove that higher performance and safety can be achieved with the ESBT, we removed the clamping network and added a base drive network. In this case, because the peak voltage is 900V, a 1200V ESBT is sufficient. Under normal operating conditions, the case temperature of the ESBT reaches 48℃. Test results show that low VCE(sat) and high-speed switching performance can reduce power consumption by 6W and improve overall energy efficiency by 3%.

　　Further Improvement Schemes

　　By redesigning the transformer and increasing the flyback voltage, the design can be further improved. In the latter case, using a 1.5kV ESBT, the power switch can withstand the ultra-high voltage stress of 1300V. In the latter case analysis, the ESBT operates at a lower temperature (42°C) than in any other case if the same heat sink is used. Because the turns ratio is changed, the stress on the secondary side of the converter is greatly reduced, and because a synchronous rectification circuit is used, a lower-priced, higher-performance 60V FET can be used to replace the 100V FET.

　　The purpose of the emitter switching study is to find the best balance between switching loss and conduction loss (mainly for high voltage applications). The main structure of the emitter switch includes a high voltage power bipolar transistor and a low voltage power MOSFET transistor that drives the bipolar transistor. The two transistors are connected in series, as shown in Figure 1. This structure requires two power supplies : the first power supply supplies current to the base of the power bipolar transistor, and the second power supply supplies the gate of the power MOSFET. Although the base of the power bipolar transistor does not require a proper drive circuit, it is necessary to apply a proper bias to the base to saturate the power bipolar transistor, so the main conduction loss is the sum of the VCE (sat) loss and the input loss of the power bipolar transistor.

　　If the power supply of the power MOSFET transistor is turned off, the leakage current immediately drops to zero, so that the output current changes the current path to ground through the base of the transistor, and this process continues until all minority carriers have moved out of this area and the bipolar transistor structure automatically turns off. This turn-off feature causes the charge stored in the base to be removed quickly, thus reducing the storage time, and most importantly, this structure is basically free of the tail current characteristic inherent in bipolar transistors. This configuration extends the safety limit of the reverse operating region by improving the ability to resist the breakdown voltage on the secondary side. In fact, because the emitter is an open circuit, there is almost no current blocking under the emitter (current blocking can cause hot spots).

　　The first ESBT (Emitter Switched Bipolar Transistor) products were hybrid structures, with specially customized power bipolar transistors assembled in a specially designed 4-pin package, connected in a hybrid series configuration. Integrating a low voltage power MOSFET transistor in this monolithic circuit structure is a major challenge in the ESBT design, especially integrating the power MOSFET transistor in the emitter area of ​​the bipolar transistor module, which is even more difficult to produce a sandwich structure. Although the entire switch is composed of two transistors connected in series, due to the solution adopted, the silicon area is only related to the size of the bipolar transistor (BJT). As

　　shown in Figure 2, two buried layers are used for the emitter and base regions respectively. In fact, since the emitter of the BJT transistor happens to be in the same area as the drain of the low voltage power MOSFET transistor, the buried layer must be properly selected to achieve the required current capability and gain of the BJT and the required breakdown voltage of the power MOSFET transistor. Therefore, a DMOS structure is diffused on a high resistivity buried layer, covering the highly doped emitter region (N-BL). From the perspective of diffusion and deposition layers, the DMOS structure is very similar to the structure of a standard low-voltage power MOSFET transistor, even if the layout of the DMOS structure matches the emitter geometry of the bipolar transistor. Finally, the base contact is placed on the diffusion layer, and the depth needs to reach the base buried layer (P-BL). It should be pointed out that the P-well region under the base contact together with the integrated DMOS constitutes a redundant lateral parasitic insulated gate bipolar transistor IGBT. In fact, due to the characteristics of the emitter switching configuration (a constant voltage is always applied to the base), this IGBT is always in the on state, thus greatly reducing the current handling performance of the ESBT. In order to prevent this harmful phenomenon, it is necessary to add a deep well with appropriate doping level, size and distance from the DMOS.

　　Quasi-Resonant Flyback Topology and Applications with ESBT

　　After the success in high-end industrial applications, we shifted the focus of ESBT development to low-end applications such as laptop adapters, printer power supplies and LCD TV switch power supplies. One of the most prominent and simplest ways to improve energy efficiency is to operate the flyback converter in QR (quasi-resonant mode). The QR flyback converter is a variable frequency version of the standard flyback converter. There are several advantages to using this topology: The QR method uses the otherwise harmful parasitic leakage capacitance to create a zero voltage condition that minimizes the conduction losses of the switch.

　　Variable frequency operation is inherent in this function. The main advantage is related to conducted EMI. In simple terms, the QR flyback structure works by performing so-called valley switching, i.e., turning on at the lowest voltage during the resonance period after the core is demagnetized. The conduction losses are calculated according to the equation Eon = CV2, where V is the on-state voltage and C is the parasitic capacitance. It is best if the switch turns on at zero voltage. Zero voltage switching is achieved by choosing the flyback voltage equal to the input voltage. However, this configuration will cause a large voltage stress on the chip. For a normal offline converter, this voltage can reach 1200V (if there is no clamping circuit) under normal transformer leakage inductance conditions. Regardless of the rated voltage and current, the ESBT has a low voltage drop and excellent switching performance, so the ESBT is the most cost-effective converter solution.

　　We redesigned a 180W, 19V single output adapter by changing the 600W power MOSFET transistor of the main switch to a 1200V ESBT transistor and removing the clamping network in the original design. The power MOSFET voltage stress is much higher than the rated breakdown voltage, so avalanche and unsafe operating conditions may occur. The 600V breakdown voltage was chosen because of the need for extremely low RDS(on) (high energy efficiency). To prove that higher performance and safety can be achieved with the ESBT, we removed the clamping network and added a base drive network. In this case, because the peak voltage is 900V, a 1200V ESBT is sufficient. Under normal operating conditions, the case temperature of the ESBT reaches 48℃. Test results show that low VCE(sat) and high-speed switching performance can reduce power consumption by 6W and improve overall energy efficiency by 3%.

　　Further Improvement

　　The design can be further improved by redesigning the transformer and increasing the flyback voltage. In the latter case, using a 1.5kV ESBT, the power switch can withstand the ultra-high voltage stress of 1300V. In the latter case analysis, the ESBT operates at a lower temperature (42°C) than in any other case if the same heat sink is used. Because the turns ratio is changed, the stress on the secondary side of the converter is greatly reduced, and because a synchronous rectification circuit is used, a lower-priced, higher-performance 60V FET can be used to replace the 100V FET.