Non-traditional MOSFET solutions to improve power efficiency of power CMOS devices

People are keen on improving density and performance by shrinking transistors. It is a wonderful thing to have faster speed and larger memory at the same cost! More and more advances in technology have enabled the perfect feature size to be upgraded to the 90nm technology node. However, the need to meet leakage and performance at deep nanometer sizes has quickly put traditional transistors in a dilemma. To continue to upgrade performance, people are using new materials and structures to improve traditional CMOS processes. In technologies beyond 32nm and above, facing unprecedented challenges in power performance, can transistors be developed through a series of leapfrog innovations? Although the answer is still being explored, new materials and device structures, from metal/high-K gate stacks, new strained silicon to multi-gate devices, are competing to initiate this revolution.

Tiny transistors consume energy when they are busy switching, so packing more transistors into the package to increase density doesn’t work. The energy consumption of different processes can be measured by dynamic power:

Dynamic power = CVdd2F

C = device capacitance

Vdd = supply voltage

F = switching frequency

Furthermore, as imperfect switches, they leak current even when they are off, which contributes to standby power consumption.

Standby power consumption = I leakage x Vdd

Ileakage = leakage current

When you pack a billion transistors into a 100mm2 die, power consumption quickly increases, and it’s getting worse. Managing power consumption is now an overriding activity for everyone from systems to design to process. Reducing power consumption is not hard, the hard part is balancing it with performance.

Short Channel Electrostatics

Due to process and material limitations, in our rush to shrink gate and channel dimensions, the upgrade of source/drain junctions and gate dielectrics has not kept pace. This results in less short channel electrostatics, and when the device is turned off, the gate has a weaker effect on the source-drain leakage (i.e., subthreshold mode). As the channel charge distribution between the gate and the source/drain beyond the normal limit increases (as shown in Figure 1), it will lead to an increase in subthreshold leakage, which can be reflected in the unexpected reduction of threshold voltage (Figure 2).

Figure 1: Effects of device charge distribution for three scenarios: (a) uniform channel doping; (b) ultra-shallow junction; and (c) high container implant doping.

Figure 2: Plots of device threshold voltage (VT) and source/drain leakage as a function of gate length (Lg). For smaller Lg, the onset of short channel effects causes VT to decrease. This is accompanied by an exponential increase in source-drain leakage. To mitigate this, we can make the source and drain junctions (xj) shallower and steeper (Figure 1b) or by increasing the channel doping around the junctions to shield the electrostatic effects on the source/drain (reducing the depletion width) (1c). Since low impedance ultra-shallow junctions are particularly challenging, we increase the channel doping significantly to suppress leakage when scaling. Increasing doping has two undesirable side effects, causing a sharp decrease in the on/off current (Ion/Ioff) ratio, which should be maximized for good switching. By achieving a low subthreshold swing (S), the electrostatic on/off ratio can be maximized (Figure 3). A simple one-dimensional description of S for a MOS capacitor ignores the effect of the charge distribution in the source/drain given by [1]:

S = 1/(subthreshold slope) = 2.3 kT/q (1 + Cdm/Cox) ~ 2.3 kTq (1 + 3Tox/Wdm)

T = Temperature

Cdm = loss capacitance

Cox = Gate capacitance

Tox = Gate dielectric thickness.

Wdm = channel loss width

S measures how well the gate swings between closing and opening the channel, depending on the capacitive coupling between the gate and the channel (Cdm/Cox). Increasing the channel doping without a corresponding reduction in the gate dielectric thickness (Tox) results in an increase in S. For short channel MOSFETs , S can also be increased by charge sharing between the gate and the short channel, which is also affected by the termination voltage. Obviously, S is minimized in the absence of channel doping (Cdm~0) while maintaining good short channel control (i.e., minimized source/drain gate charge sharing). Without complete freedom to scale gate dielectric thickness and junction depth, minimizing S is a daunting proposition for bulk MOSFETs , as short channel control then becomes extremely dependent on increasing channel doping.

Figure 3: Subthreshold behavior between two devices with matched currents but different subthreshold slopes.

Another high cost of doping is the loss of transmission speed. Devices with high channel doping are forced to operate at higher gate electric fields. This increases the scattering of channel carriers at the gate-dielectric interface, resulting in a significant decrease in carrier mobility (Figure 4) and a compromised drive performance.

Figure 4: Electron mobility of a MOSFET as a function of the effective electric field for different channel doping levels (NA) and temperature [2].

Ultra-thin devices

Silicon-on-insulator (SOI) heterostructures create opportunities to build devices with ultra-thin silicon bodies (silicon thickness Tsi < 10 nm) (Figure 5). Ultra-thin SOI provides an alternative means of controlling short channel effects through the natural electrostatic barrier established by the silicon-dielectric interface. The source/drain junction depth is now naturally shallower due to the constraints of the ultra-thin silicon channel.

Figure 5 shows a transmission electron microscope (TEM) image of a 40nm-Lg fully depleted ultra-thin (UT) SOI device with metal gate and high-K gate dielectric. Unlike bulk transistors , ultra-thin SOI improves short channel electrostatic effects through their body structure, which reduces their dependence on channel doping (Figure 6). Channel doping processes are used to control leakage in the smallest body transistors to prevent it from growing to uncontrollable levels, which can be calculated by using thin Si. Since the loss capacitance Cdm is kept to a minimum, the ratio of on/off current can be maximized by reducing S.

Figure 6 shows a comparison between the channel doping required for bulk MOSFET and ultra-thin (UT) SOI to achieve the same short channel control for a given Lg (SG: single gate; DG: double gate; PD-SOI: partially depleted SOI).

With low or no channel doping, the threshold voltage of such a device can be determined primarily by the gate and dielectric materials. Since the equivalent channel depletion width, Wdm, is larger than Tsi, the channel is fully depleted. By forgoing the use of channel dopants to control short channel effects, fully depleted SOI devices can operate at reduced effective electric fields, where carrier mobility is higher (Figure 7).

FIG7 FD-SOI devices can operate at lower effective electric fields with higher mobility compared to equivalent bulk transistors.

Eliminating channel doping also reduces variability due to random dopant fluctuations. Despite variations in thin Si body thickness, FD-SOI devices show greatly improved device-to-device matching compared to doped body devices (Figure 8). This is important for SRAMs with increasing memory densities and analog technologies that are subject to random variations.

Figure 8: Mismatch comparison between FD-SOI and other equivalent devices from different processes (PDSOI: partially depleted SOI). FD-SOI’s immunity to floating body effects and minimized source/drain (S/D) junction capacitance (Cj), combined with metal gate and high-K dielectric, offer several advantages for low-power and mixed-signal applications, including reduced gate leakage, good linearity, and low noise [3] (Figure 9).

Figure 9: FD-SOI devices show lower noise compared to PDSOI devices.

Strained silicon and enhanced transmission properties

By improving the effects of short channel electrostatics, leakage, variability, and standby power are reduced. To some extent, it even improves the transfer characteristics. However, to sufficiently reduce dynamic power without having to compromise leakage and performance, further enhancements to the transfer characteristics are needed.

Since dynamic power consumption depends quadratically on Vdd (CVdd2F), adjusting the supply voltage is the most effective way to reduce dynamic power . However, if the threshold voltage is not reduced, then the reduction in Vdd will lead to a significant loss of carrier density (Qi) in the transistor.

Qi(max) ~ Cox (Vdd-VT)

Since source/drain leakage depends exponentially on VT (Figure 2), adjusting VT becomes very limited. In addition, the increase in Cox is limited by Tox, which is ultimately limited by gate leakage and dielectric reliability. A similar problem arises when transistors are stacked to reduce leakage (Figure 10). Stacked devices in a logic block have a reduced virtual node (Vdd'-VT) for maximum gate overdrive, so they become weaker as the stack increases.

Figure 10: Transistor stacking is common for implementing “sleep” transistors and power gating techniques.

To recover the same current (I = Qi rate), the carrier rate (or mobility) must be increased to compensate for the Qi losses. This is where mobility is enhanced with strained silicon.

With Intel announcing the combination of stressed substrate materials and SiGe source/drains at the 90nm technology node, strained silicon for different processes has been integrated into products to enhance their CMOS devices [4]. In addition, many other approaches have been investigated, from dual stress substrates to low-strained silicon. The fundamental goal of driving transistor performance is the same: to substantially enhance mobility, we can maintain circuit performance while trading off drive current for reduced dynamic power consumption (Figure 11).

Figure 11: Oscillator circuit simulations show that the average power consumption can be reduced by reducing Vdd from 1.2V to 1V while maintaining frequency performance while improving mobility.

This means that mobility improvements—the traditional driving force behind the development of high-performance transistors—are also beginning to shift to the frontier of low-power management, so scaling paths to higher mobility need to be investigated. Combining and enhancing the strengths of existing strained materials through process technology is a natural way to further improve performance (Figures 12, 13) [5]. Ultimately, non-silicon materials with higher mobility may be needed in addition to strained silicon, leading process and design engineers to work hard to develop new processes and address various design complexities.

Figure 12: The combination of strained silicon directly on an insulator (substrate strain) with embedded SiGe source and drain and substrate stress material enables the realization of a hybrid strained PMOSFET.

Figure 13: NMOSFET performance enhanced by strained silicon fabricated directly on an insulator (substrate strained silicon) with a combined stress liner.

The improvement in mobility finally paid off. The increase in Lg and channel mobility accelerated the reduction in transistor channel resistance (Rch), while the parasitic source/drain and contact resistance (Rsd) decreased at a slower rate. As the parasitic parameters caused more and more voltage drops, increasing the Rsd/Rch ratio led to a gradual offset of the enhanced transistor performance despite the increase in mobility (Figure 14) [6]. This meant that new processes that dramatically reduced parasitic resistance had to be developed simultaneously with the improvement in mobility to avoid mutual cancellation.

Figure 14: Increased drive current due to mobility enhancement and Rsd/Rch as a function of Lg strained silicon accelerates the growth of Rsd/Rch, resulting in a gradual decrease in return drive current.

Conclusion

We find that improving electrostatics and transistor transfer contribute to a sophisticated approach that reduces both active and standby power consumption . To do this, new transistor structures and materials expand the performance-power design space beyond traditional bulk silicon transistors . Ultimately, transistor innovation will continue to play a key role in defining the next generation of strategies to improve power efficiency by forming the bottom layer of a multi-layered system-circuit-device power management ecosystem.