Development Strategy of Adaptive Frequency Modulation DC/DC Buck Converter for Automotive Electronics

At present, high-frequency and high-efficiency DC/DC converters are increasingly used in automotive electronic systems. High switching frequency can use smaller power inductors and output filter capacitors, thereby reducing the size of the system, improving compactness and reducing costs. High working efficiency can extend the service life of the car battery, reduce system power consumption, thereby reducing heat generation, optimizing the thermal design of the system and further improving reliability. However, high switching frequency will reduce the working efficiency of the system. Therefore, when designing DC/DC buck converters for automotive electronic applications, some compromises must be made between switching frequency and working efficiency.

The maximum switching frequency of the DC/DC buck converter is limited by the maximum input voltage of the DC/DC, the minimum output voltage and the minimum on-time of the power tube. The theoretical limit can be calculated by the following formula:

Formula 1

Where fSW(MAX) is the maximum switching frequency, tON(MIN) is the minimum on-time required by the switch tube, VD is the forward voltage drop of the freewheeling diode, VOUT is the input voltage for normal operation, and VSW is the on-voltage drop of the switch tube. The above formula shows that when tON(MIN) is constant, a low duty cycle requires a lower switching frequency to ensure safe operation of the system. Similarly, a low switching frequency allows a lower output-to-input voltage ratio. The main reason why the input voltage depends on the switching frequency is that the PWM controller has a minimum on-time tON(MIN) and off-time tOFF(MIN). If the value is 100ns, that is, the on-time of the switch tube when it is turned on must last at least 100ns. If it is less than 100ns, the power tube MOSFET may not be turned on normally. Similarly, the off-time when the switch tube is turned off must last at least 100ns. If it is less than 100ns, the MOSFET may not be turned off normally. This means that the minimum and maximum duty cycles are:

Formula 2

Here fSW is the switching frequency, tON(MIN) is the minimum on-time and tOFF(MIN) is the minimum off-time.

The above formula shows that when the switching frequency is reduced, the range of the duty cycle increases. The input and output voltage range can also be increased. The optimized switching frequency can ensure that the system has a sufficiently wide input operating voltage range while the inductor and capacitor values ​​are as small as possible.

Usually the input voltage of DC/DC power supply chip has a rated operating voltage range. In addition to the rated operating voltage limit, the actual input voltage is also subject to some other conditions. The minimum actual input operating voltage is usually determined by the maximum duty cycle. When the input voltage is the highest, the duty cycle is the smallest, so under the condition of a certain output voltage, the maximum actual input operating voltage is determined by the minimum duty cycle of the PWM controller. tON(MIN) is the shortest duration that each controller can turn on the high-end MOSFET. It is determined by the internal timing delay and the amount of gate charge required to turn on the high-end MOSFET. Applications with low duty cycles can approach this minimum on-time limit.

Usually the switching frequency of DC/DC power chips is fixed, but if we can reduce the switching frequency when the input voltage increases, we can expand the duty cycle range, thereby expanding the input voltage range while ensuring the output voltage accuracy. In many DC/DC power chips, a resistor is connected to the ground through a pin to set the DC/DC switching operating frequency. A typical application circuit is shown in Figure 1.

Figure 1: A typical DC/DC application circuit

The RT pin of LT3980 is connected to the ground with a 97.6K resistor, setting the operating frequency of LT3980 to a fixed 400KHz. When the RT resistor is 32.4K, the operating frequency is 1MHz. In this DC/DC converter that uses an external resistor to set the switching frequency, a voltage regulator Z1 and a current limiting resistor R1 can be added to reduce the switching frequency when the input voltage increases.

Figure 2: Typical circuit for adjusting DC/DC regulator using external resistors and Zener diodes

At high input voltage, the output current and voltage ripple increase because the frequency decreases and the inductance value is constant. When the frequency changes in a wide range, the inductor cannot work optimally and the loop compensation cannot be optimized. In this way, we need to add R2 and Z2 to the circuit in Figure 2 to limit the frequency change range. The external resistor method requires careful calculation by the system engineer and is easily affected by parasitic parameters. Here, we use the internal circuit to detect the change of input voltage and automatically adjust the switching frequency to simplify the application circuit design.

(I) DC/DC step-down transformer in current control mode

Figure 3 is the structure of the DC/DC converter system in voltage control mode. Among them, EA is the error amplifier, PWM is the PWM comparator, Soft start is the soft start module, Band gap reference is the band gap reference source, OSP is the frequency reduction protection circuit, Oscillator is the oscillator, Logic Latch is the logic trigger, Driver is the driving circuit of the driving switch tube PMOS, OCP is the overcurrent protection, UVLO is the undervoltage protection, and OTP is the overheat protection.

Figure 3: Block diagram of a voltage-controlled DC/DC buck converter

The circuit adopts a voltage-type PWM control mode with a frequency reduction function, and the output voltage error is small. In the figure, the PWM control part is composed of an error amplifier and a PWM comparator. After the feedback voltage is compared with the reference voltage, the difference is amplified to generate an error signal, and after a certain zero-level point compensation, it is provided to one end of the PWM comparator input. At the same time, the other end of the comparator input is a pulse clock signal of a certain frequency provided by the oscillator circuit.

This signal will be transmitted to the logic circuit part of the back end, which includes RS triggers and related logic containing various protection signals. It controls the state of the power switch by turning on and off the drive circuit, thereby setting the operating frequency of the converter and the maximum duty cycle of the power tube. The main function of the OSP comparator in the figure is to control the oscillator through the OSP signal to reduce the clock signal at the input of the PWM comparator when the output voltage is too low and the efficiency decreases, thereby improving the conversion efficiency of the converter under the same circumstances.

The circuit uses dual power supplies. Vdd is converted from the input voltage Vcc through a high-voltage linear regulator to 3.3V. Vcc is the input high voltage, which is used to supply the enable hysteresis circuit, bandgap reference source, Vdd generation circuit, overcurrent protection and drive circuit. The MOS tubes in these circuits use high-voltage DMOS devices to prevent breakdown; other circuits that are not related to the input voltage are supplied with Vdd, and the MOS tubes in them use CMOS devices.

Currently, the peak current control mode DC/DC converter is more widely used, and its principle block diagram is shown in Figure 4.

Figure 4: Block diagram of a peak current control DC/DC buck converter

Corresponding to the voltage control mode, the DC/DC converter in the current control mode adjusts the output current of the DC/DC with an almost infinite open-loop gain, which is actually a current source with high output impedance. As shown in Figure 4, in the DC/DC buck converter in the current control mode, the fast high-gain current loop and the slow voltage control loop are nested. The inductor current is compared with the sawtooth wave synthesized signal after slope compensation and the voltage error signal to generate a control signal. When the output voltage drops, the power tube is controlled to open to provide more current to the load to keep the output voltage stable. The DC/DC in the current control mode measures the inductor current and changes the output into a constant current source output, so that the output stage of the DC/DC is transformed from a two-pole system in the voltage mode to a single-pole system, which makes it easier to compensate and improves stability.

(II) Oscillator design

Oscillator circuits are widely used in DC/DC integrated circuits. The oscillation clock provides synchronization of switching pulses for the internal circuits and derives a sawtooth wave to provide to the PWM comparator. It is the basic unit of voltage mode and current mode DC/DC converters. Figure 5 shows the oscillation circuit designed in this paper. The design adopts a constant current charge and discharge structure. The charging current is I1+I2 (I1 when frequency is reduced) and the discharge current is I12+I13 (I12 when frequency is reduced).

Figure 5: Oscillation circuit with controlled oscillation frequency

As can be seen from Figure 5, M1 and M2 are capacitor charging, and M9 is capacitor discharging, which determines the clock frequency of the oscillator.

First, assume that the output oscillation voltage is proportional to the charge and discharge current. Based on this assumption, the bias current can be determined. If the desired frequency is 800K (T=1.25us), the rise time is 90% of the total cycle (1.125us), and the peak-to-peak value Vp-p of the output sawtooth wave SAW is required to be 1V. Then, the charging current is

Formula 3

Where C is the capacitance value of C1 and T is the oscillation period.

As can be seen from the circuit diagram, the turning point of the oscillation waveform can be determined by the following formula:

Equation 4

FIG6 is the output waveform of the oscillator. It can be seen from the figure that the oscillation waveform fluctuates within the range of 0.6V to 1.8V, which meets the design requirements.

Figure 6: Oscillator output waveform

When the output-input voltage ratio is lower than a certain value (0.2), it means that the duty cycle of the control pulse is very low and the efficiency is reduced. At this time, the OSP signal is generated through the low ratio protection circuit to reduce the frequency of the overall circuit. As can be seen from the circuit diagram, when OSP becomes a high level through the control circuit, M0 is closed, and the width-to-length ratio of M1 and M2 is 4:1. At this time, the charging current becomes 1/4 of the original, and the charging time becomes 4 times the original. In this way, the frequency of the output oscillation wave becomes 1/4 of the original, that is, 200KHz, which improves the conversion accuracy of the power supply.

(III) Application

In automotive electronic applications, the input voltage includes multiple voltage rails such as 12V, 24V and 36V. Under the condition of determining the output voltage, this DC/DC that can adaptively adjust the operating frequency according to the input voltage can automatically set the appropriate operating frequency, optimize the working efficiency of the DC/DC, and reduce transient processes.