Ten Questions about LDO (Low Voltage Regulator)

1. What is an LDO regulator?

The LDO low dropout regulator (LowDropoutRegulator) is a classic voltage regulator that can achieve a smaller input/output voltage difference than the traditional three-terminal fixed voltage regulator. Ideally, the LDO can provide a fixed or adjustable output voltage that does not change over time and temperature, and is not affected by line and load changes.

2. What are the main selection criteria for LDO?

Input voltage range; output voltage, fixed or adjustable; output accuracy over line, load, and temperature; load current requirement; dropout voltage; power supply rejection ratio (PSRR); output noise; quiescent current and shutdown current.

3. Does the value of the output bypass capacitor affect the performance of the LDO?

LDO designs are usually optimized for specific values ​​of load bypass capacitance. Increasing the load capacitance above the recommended value can improve the load transient response. However, when a larger value of output capacitance is selected, the value of the input bypass capacitance should also be increased accordingly. Please note: The input and output capacitors should be placed as close to the LDO as possible.

4. What types of capacitors can be used as input/output bypass capacitors?

Any good quality ceramic capacitor can be used as a bypass capacitor as long as they meet the minimum capacitance and maximum effective series resistance (ESR) specifications listed on the LDO data sheet. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because they have good temperature stability and very low voltage coefficients.

5. Does the ground current of the LDO change with the load current?

As the output load increases, designs using bipolar transistors as pass elements will show a larger ground current variation, up to 5% of the load current. LDO-based MOSFETs are more power efficient because their ground current increase with load is minimized, typically less than 0.1% at full load.

6. What is Power Supply Rejection Ratio (PSRR)?

The power supply rejection ratio (PSRR) indicates the ability of an LDO to prevent the output voltage from fluctuating when the input voltage changes.

The PSRR value is usually specified at a specific frequency, such as 60dB PSRR at 120Hz. Battery-powered systems should use LDOs to maintain a high PSRR when the battery voltage is low (i.e., low input-output voltage difference).

7. If the LDO is driven by a switching power supply, can the high-frequency switching noise be suppressed?

LDOs can suppress input noise of tens or even hundreds of kHz. High-frequency (above 1MHz) switching noise is mainly suppressed by the output bypass capacitor network; above 1MHz, the loop bandwidth of the LDO is too low to provide any noise attenuation. The LDO forms an impedance divider with the pass element, the output capacitor network, and the load, which can provide noise suppression at high frequencies.

8. What are the causes of LDO output noise and how to reduce it?

The voltage reference inside the LDO is the main source of output noise. It is usually expressed in microvolts RMS over a specific bandwidth, such as 25μV RMS over the 1 to 100kHz range. This low level of noise is much lower than the switching transients and harmonics of the DC/DC converter.

Some LDOs have a capacitor from the bypass pin to ground to filter out reference voltage noise. Following the data sheet specifications for input, output, and bypass capacitors will eliminate noise level issues.

9. Does the LDO have a minimum load current requirement?

None of ADI's LDOs require a minimum load current.

However, many competitive LDO products on the market do have minimum load current requirements, some as high as several mA.

10. What are the key features to consider when selecting an LDO?

Includes an enable input to turn the LDO on and off to save system power; programmable soft-start to limit inrush current, control output voltage rise time, and implement voltage sequencing during startup; a tracking function that allows the LDO output to follow an external voltage rail or reference voltage; a bypass pin that allows an external capacitor to reduce output voltage noise and improve power supply rejection; a power good output to indicate that the output is in regulation; thermal shutdown to shut down the LDO when the temperature exceeds a specified level; and a current limit function to control the LDO output current and power consumption.