How will 3D integrated circuits be realized simultaneously?

　　The first commercial applications of 3D ICs, CMOS image sensors and stacked memory, will begin before the full infrastructure is built. In Part I, we will review the powerful drivers behind 3D integration and the current state of the infrastructure supporting the technology, while in Part II (next issue), we will explore the commercialization of 3D IC technology. There is a perfect storm underway that will

　　require a shift in how the industry implements microelectronic functions, both at the device level, where gate and interconnect delays are a concern, and at the system level, where bandwidth and timing issues are a concern. Key factors influencing this shift include the delay of the International Technology Roadmap for Semiconductors (ITRS) and the continued shrinking of copper and low-k wire dimensions due to the difficulty of integrating porous low-k materials. At the same time, up to 50% of power consumption is used in the interconnects of the chip, and even for copper interconnects at the 65nm process node, lead resistance and parasitic capacitance have become issues.

　　These issues were first recognized in 2001, when IEEE Fellows Saraswat, Rief, and Meindl predicted that "chip interconnects may slow or halt the historical development of the semiconductor industry..." and proposed that 3D integration of circuits should be explored.

　　In September 2007, the Semiconductor Industry Association (SIA) announced that "the ability to reduce transistor size will be limited by physical limits within the next 10-15 years or so," so the need for 3D integration became more apparent. Entirely new device structures, such as carbon nanotubes, spintronics, or molecular switches, will not be ready for another 10-15 years. 5 New assembly methods, such as 3D integration technology, have been proposed again. The

　　memory speed lag problem is another driver of 3D integration. It is well known that memory access speeds have developed slowly relative to processor speeds, causing processors to be delayed while waiting for memory to retrieve data. This problem is exacerbated in multi-core processors, which may require direct bonding of memory to the processor.

　　The Rescue of 3DIC Integration Technology

　　When ICsGoingVertical was published in February 2005, few readers were aware of the technological advances taking place in 3DIC integration. They thought the technology was just lamination and wire bonding, a back-end packaging technology.

　　Today, 3D integration is defined as a system-level integration structure in which multiple layers of planar devices are stacked and connected in the Z direction via through-silicon vias (TSVs) (Figure 1).

　　To manufacture such a stacked structure, many processes have been developed, and the following are the key technologies:

　　■TSV production: Z-axis interconnection is a connection that penetrates the substrate (silicon or other semiconductor materials) and is electrically isolated from each other. The size of TSV depends on the data acquisition bandwidth required on a single layer;

　　■Layer thinning technology: Initial applications need to be thinned to about 75~50μm, and in the future it needs to be thinned to about 25~1μm;

　　■Alignment and bonding technology: either between chip and wafer (D2W) or between wafer and wafer (W2W).

　　By inserting TSV, thinning and bonding, 3DIC integration can save a large part of the packaging and interconnection process. However, it is not yet fully clear where these need to be integrated in the entire manufacturing process. It seems that for the TSV process, it can be obtained through IDM or wafer fab during IC manufacturing and thinning, while bonding can be achieved by IDM or by external semiconductor assembly and test providers (OSATS) in packaging operations, but this may change when the technology matures.

　　What is likely to happen in the future is that 3DIC integration technology will start when the development path between IC manufacturing and packaging overlaps.

　　3D process selection

　　TSV can be made during IC manufacturing (viafirst) or after IC manufacturing is completed (vialast). In the former case, the front-end interconnect (FEOL) type TSV is made before the IC wiring process begins, while the back-end interconnect (BEOL) type TSV is implemented in the IC manufacturing plant during the metal wiring process.

 

　　FEOL-type vias are fabricated on a blank silicon wafer before any CMOS process begins (Figure 2). The conductive material used must be able to withstand the thermal shock of subsequent processes (usually above 1000°C), so only polysilicon can be used. TSVs made during the BEOL process can use metal tungsten or copper, and in general, the manufacturing process is early in the entire integrated circuit process to ensure that TSVs do not occupy valuable interconnect wiring resources. In both FEOL and BEOL cases, TSVs must be designed into the IC wiring.

　　 TSVs can also be made after the CMOS device is manufactured. It can be completed before the bonding process, or after the bonding process. Since the CMOS device has been manufactured, the wafer does not need to be subjected to high temperature processing when the via is formed, so copper conductive materials can be used. Obviously, the blank area for making these vias needs to be considered when designing the chip.

　　If a choice is available, making TSVs in a foundry is a relatively simple option, whether it is a FEOL or BEOL approach. The BEOL interconnect layer is a complex mixture of different dielectric and metal layers. Etching through these layers is difficult and product-specific. Making TSVs by etching through the BEOL layers after full IC fabrication blocks routing channels, increases routing complexity and increases chip size, possibly requiring an additional routing layer. Now that foundries such as TSMC (Taipei, Taiwan) and Chartered (Singapore) have announced their intention to mass-produce TSV fabrication, making the vias in the IC manufacturing process will become a more viable option.

　　Thinning

　　In most 3DIC processes, the thickness of a single IC is well below 75μm. There are two options for thinning the device wafer (Figure 3). In process A, wafer 2 is bonded directly to the IC stack face-down. The wafer is then thinned to the required thickness, possibly exposing the backside of the TSVs. Backside processing sequentially etches through-holes (if not implemented in the wafer fab) and creates backside I/O pads. Such stack thinning also allows for face-down die stack bonding using known good die (KGD) instead of the entire wafer.

　　In process B, the wafer is first bonded to a temporary carrier wafer, usually a silicon wafer or a glass wafer, followed by thinning and backside processing. The IC wafer is bonded with the front side facing the carrier wafer, and must be bonded to the 3DIC stack with the front side facing up later. Since the temporary bonding of the wafer to the carrier wafer is done with an organic adhesive, the subsequent process steps need to be limited to the temperature range in which the organic adhesive is stable.

　　After thinning and final backside processing, the device wafer can be aligned and bonded to the stack and then separated from the carrier wafer (wafer-to-wafer bonding), or the device wafer can be released directly from the carrier wafer onto the dicing tape of the dicing frame and KGD can be performed.

　　W2W is most suitable for wafers with high single-wafer yield and uniform chip size, such as memory. D2W bonding is used for wafers with low single-wafer yield and/or different chip sizes. Since the whole wafer cannot be used for low-cost processing after D2W bonding, it is critical when the D2W assembly is completed.
　　Forming Through Vias

　　There are two main technologies for "drilling" TSVs, one is dry etching or Bosch etching, and the other is laser ablation (Table 1). Developed for more than ten years for the MEMS industry, the Bosch process rapidly cycles between SF6 plasma etching to remove silicon and C4F8 plasma deposition steps to achieve sidewall passivation. As can be seen in Figure 4, the etching speed has steadily increased over the past few years.

　　In a major advance, laser technology has been used in memory stacks by Samsung (Seoul, South Korea). Most of the latest data comes from Alexey Rodin and colleagues at Xsil (Dublin, Ireland). As a maskless process, laser processing avoids the process steps of photoresist coating, photolithography exposure, development, and stripping. However, there are still some questions about whether laser drilling can be further reduced when TSV dimensions drop below 10μm in the future. Via

　　insulation

　　Oxide (SiO2) insulation layers are usually deposited by CVD processes using silane (SiH4) or TEOS. If TSVs are insulated and filled after chip manufacturing, the deposition temperature needs to be carefully selected. Typical TEOS deposition temperatures are in the range of 275-350°C to obtain a functional insulation layer with appropriate density.

　　Applications such as CMOS image sensors and memory require lower deposition temperatures. Alcatel (recently acquired by Tegal, Petaluma, California) and other equipment manufacturers have recently developed such low-temperature oxide deposition technologies. IMEC (Leuven, Belgium) has reported the use of Parylene precursors, which can be deposited at room temperature and can be used as a highly efficient organic insulating layer for TSVs.

 

　　Barrier, Seed and Fill Plating

　　The performance of barrier, seed and plating techniques depends on the size and aspect ratio (AR) of the via. It is important to understand the required aspect ratio for different via sizes, whether considering blind vias or via filling. Most cost of ownership (CoO) models show that via production and via filling are the main cost barriers to 3D integration, but this is obviously dependent on via size, pitch and aspect ratio. Although equipment vendors and material suppliers are working on aspect ratios of 10:1 to 20:1, it is not clear in which applications such aspect ratios will be used in the short term.

　　Research by Amkor (Chandler, Ariz.) shows that using thinner circuit layers, combined with smaller via sizes, can achieve lower CoO because these lower aspect ratio vias are less expensive to manufacture (Figure 5).

　　As 3D technology evolves and the size and pitch of vias in applications shrink, the thickness of each layer in the stack is likely to decrease. Testing to date shows that circuit performance will not deteriorate even if the silicon thickness is reduced to less than 5μm. Therefore, it is likely that manufacturability rather than electrical performance will be the limiting factor in the future. In addition, thickness becomes important when considering via-first or via-last schemes. The latter requires an additional 6μm thick back-end dielectric layer to be etched before the silicon etch begins. For thin silicon layers, this will have a significant impact on the aspect ratio of the etch.

　　3D applications such as CMOS image sensors, memory, and memory on logic circuits will not require aspect ratios greater than 5 for the next 2-3 generations. We will not see aspect ratios in the 10-20 range until TSV dimensions drop to about 1μm or even smaller.

　　In copper vias, both the TiN adhesion/barrier layer and the copper seed layer are deposited by sputtering. However, conventional PVD DC magnetron technology is not satisfactory for achieving high aspect ratio (AR>4:1) step coverage. PVD technology based on ionized metal plasma (IMP) enables uniform deposition of copper seed layers on the sidewalls and bottom of the via. IMP provides better step coverage and barrier/seed layer uniformity due to the directionality of the deposited atoms and the use of ion bombardment in the process of sputtering material from the bottom of the via to the sidewalls.

　　Wafer Bonding Technology Selection

　　Wafer bonding technologies investigated for 3D integration include:

　　■ Oxide (SiO2) eutectic bonding

　　■ Metal-to-metal bonding

　　■ Copper-to-copper eutectic bonding

　　■ Eutectic bonding (Cu/Sn)

　　■ Bump technology (Pb/Sn, Au, In)

　　■ Polymer adhesive bonding

　　All of the bonding techniques shown in Figure 6 require extremely smooth, flat, and clean surfaces due to feature size limitations. Although all of these techniques appear to be viable, there is a trend toward metal-to-metal bonding, which allows for both mechanical and electrical contact interfaces. Copper-to-copper bonding

　　Direct copper bonding requires pressure application at 350-400°C for more than 30 minutes, followed by a nitrogen anneal at 350-400°C for 30-60 minutes. The process requires highly polished copper surfaces that are kept very clean. Commercial tools such as those offered by EV Group (St. Florian/Inn, Austria) and SUSS MicroTec (Waterbury, Vermont) require multiple bond heads on a single alignment tool to achieve acceptable throughput. A process such as that reported by Ziptronix (Morrisville, North Carolina) called direct bond interconnect (DBI) is said to significantly improve this throughput. This technology uses metal to cap the TSV, and then uses oxide and metal simultaneous CMP for flattening. After patented surface treatment technology, standard bonding/alignment machines can be used to achieve chip or wafer bonding in 1-2 minutes under atmospheric conditions. Pressure is applied at 350°C, and a single metal interface can be obtained under low CoO bonding operations.

　　3D Applications

　　Table 2 summarizes nine different 3D integration process flows, all corresponding to wafer processing all the way to bonding.

　　The second part of this article will focus on the key players in the commercialization of 3D technology. It will introduce possible application areas of 3D integration, such as memory and logic circuits, flash memory stacking, and other key directions.