Designed for low power consumption

When it comes to calculating the operating costs and carbon footprint of telecom infrastructure projects, power consumption becomes an increasingly important variable. For example, the average fully loaded 3G base station costs about $1,600 per year in the United States, or about $3,200 per year in Europe. This means that a typical European operator will consume 58MW of power to operate 20,000 base stations, which translates to about $62 million per year. In addition to these costs, the power consumption of each base station is estimated to emit 11 tons of carbon dioxide per base station per year. For these operators, power consumption is cost. FPGAs have become one of the most important components of base station architecture, so the focus of people's attention on FPGAs is to minimize power consumption.

For example, to minimize power consumption, the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, in a typical design, the ECP3 reduces static power consumption by 80% and total power consumption by more than 50% compared to competing FPGAs with SERDES capabilities.

When using FPGAs, system designers typically consider the power consumption of four parts of the FPGA:

Power consumption of a pre-programmed static (quiescent) device

Pre-programmed static device power consumption refers to the power consumption of the FPGA before it is programmed. That is, when the FPGA is powered on, but in an unprogrammed state, this is the static device power consumption. It is important that the device does not consume a large
amount of power during this period. Conceptually, the FPGA device will consume too much power and may shut down the power supply, preventing the board from successfully initializing the system. Therefore, FPGA vendors must carefully design transistors with low static power consumption without compromising areas that require higher performance (such as I/O and SERDES).

Inrush programming current: (inrush current/power consumption required to program the device until programming is completed)

In the past, inrush current programming has been an issue for FPGA vendors. Inrush programming currents actually exceed the power consumption of a typical application, as well as the actual rated power supply/regulator power. This is of course undesirable, and Lattice has invested considerable effort in designing its products so that the programming current (inrush) is below the power consumption of any typical application. Lattice accounts for and tracks inrush in the datasheet and in the Power Calculator tool.

Post-programmed static power consumption: The power consumption of the device at 'zero MHz' frequency

Post-programmed static power is a significant portion of FPGA power consumption. This is due to the large number of transistors in an FPGA (typically 8 to 10 times the number implemented with equivalent ASIC logic, not including configuration and multiplexers), all of which have a small amount of leakage current. The leakage current of these transistors (for switching multiplexers, RAM cells, etc.) is usually "always there" and absorbs power regardless of whether the transistor is being used or not. Typically, post-programmed static power consumption is equal to or greater than static device power consumption. There are some recent innovations in solving the power grid and removing the power consumption of these special transistors, which will reduce this portion of static power consumption.

Dynamic power consumption: The power consumption increased by non-zero frequency. (i.e. P = kcV2f)

Dynamic power follows the kcV2f rule and is usually under the control of the designer. Depending on the different types of designs being implemented (always on, always processing, type of data path designed vs. wake up, process and return to sleep, etc.), both dynamic power and programmed static power are the most important components in power analysis.

Power consumption is closely related to temperature. As the FPGA heats itself, power consumption increases due to increased leakage current in the transistors. In extreme cases, the device gets so hot that the transistors cannot turn off, a condition known as thermal runaway. Power analysis is considered a vital part of any FPGA design process. Using power analysis, designers can be confident that the design will work in the designed environment. Various techniques are used to control temperature such as fans, heat sinks, design modifications, I/O standards, etc.

Building a power consumption model for a "simulated environment"

In addition to improvements in FPGA architecture, software-based tools are valuable in the low-power design process. For example, the Lattice Power Calculator (Figure 1) includes a power model for the simulated environment, a graphical power display, and a variety of useful reports. The optional thermal resistor model simulates various real-world thermal conditions, including heat sinks, airflow, and printed circuit board complexity, while the graphical power curve reflects the operating temperature. After the printed circuit board is assembled, the software-based power calculator can be used before and after the FPGA design process to analyze the expected power consumption.

Figure 1 The Power Calculator can be used at any stage in the design cycle. Early estimates of switching rates can be replaced later with simulation results. An accurate Power Calculator calculates current and power consumption for all structural elements and provides thermal models to simulate real system conditions.

Summarize

Does successful low-power design depend on architecture or process? The answer is neither of the conventional wisdom holds. Advanced processes do not guarantee low power: the trade-offs made during the architecture and circuit design phases are critical to the end result. If an FPGA is optimized for performance, it will inevitably result in higher overall power consumption. Designers must make the trade-off of placing high-performance circuits where they are absolutely needed, while optimizing other areas of the chip for low power. Traditional FPGA vendors simply expect the next process node to yield measurable power savings. However, the 65nm LatticeECP3 shows that it is possible to achieve lower power consumption than competing 40/45nm devices. At the heart of this paradigm shift is clever circuit and transistor design.