Could anyone help me see what is wrong with my amplifier circuit?

飞絮

Could anyone help me see what is wrong with my amplifier circuit? [Copy link]

 

The picture below is the finished board, and the result is the same as the simulation. The purpose is that the first-stage op amp collects a current signal and sends it to the second stage for amplification. The potential of the first stage is raised by 300mV. In order to only amplify the current signal and not the basic 300mV, the negative end of the second stage is also raised by 300mV. In this way, only the potential difference at the input end of the op amp should be amplified. The potential difference in the figure is 0.02V, and it should be 0.32V after 16 times amplification, but it is actually 5V. What's going on? Where did I go wrong and how should I change it?

呜呼哀哉

If you want a direct differential amplifier structure without all the twists and turns, you can also use INA directly, add a sampling resistor to the current, and set the appropriate common-mode level.

呜呼哀哉

In addition, the output of U4B in your circuit is 0.405V, and the connection of U4C is a non-inverting structure. The 0.385V bias level you expected does not work. You want to add an inverting terminal to offset it, which is not realistic.

It feels like positive feedback.

maychang

"Where did I go wrong?"

Note that R7 and R5 are connected in parallel and can be replaced by a 500 ohm resistor. Then the amplification factor of the second stage is not 15/1+1=16 times.

飞絮

That makes sense.

gmchen

First of all, intuitively, the second amplifier must be abnormal. Because if the amplification is normal, the voltage levels of the positive and negative input terminals should be basically equal (virtual short circuit), with a maximum offset voltage of a few millivolts. Now it is 0.2V, which is obviously too large, so the output of this amplifier must be in saturation, and the output is equal to the power supply voltage.

gmchen

What the OP meant is to use the second op amp as a differential amplifier to subtract the bias voltage of the first op amp.

But that differential amplifier circuit is wrong.

The correct way is to use another op amp to buffer the bias voltage of the first op amp (i.e. make it a follower), and then connect its output to the end of R5 that was originally grounded (not grounded). In order to improve the common-mode rejection ratio, connect a resistor equal to R6 to the ground at the right end of R4 (i.e. the non-inverting input of the second op amp). In this way, the second op amp is a standard differential amplifier.

However, due to the single power supply, this circuit will have problems when the output is close to 0, because the output of the op amp cannot reach 0 completely.

gmchen

I would also like to remind you that the maximum allowable power supply voltage of the TLV2764 chip is 4V.

飞絮

Thanks for your advice, I modified the circuit. The actual 0.3V is provided by the op amp, not the resistor voltage divider. The actual op amp used is TLV274, which is not available in the simulation software, so I had to use 2764 instead. The new circuit should be correct, and the amplification factor is no longer 1+R6/R5, but R6/R5.

maychang

Feixin published on 2021-5-28 14:18 Thank you for your advice. I modified the circuit. The actual 0.3V is provided by the op amp, not the resistor divider. The actual op amp uses TLV274, and the simulation software...

Q1Q2 seems unnecessary. The purpose of using these two transistors may be to expand the current, but the output capacity of the op amp is sufficient, so there is no need to expand the current.

maychang

Feixin published on 2021-5-28 14:18 Thank you for your advice. I modified the circuit. The actual 0.3V is provided by the op amp, not the resistor divider. The actual op amp uses TLV274, and the simulation software...

In addition, there is no need to use U4D. First use U4A to follow, then use Q1Q2 to expand the flow, and then use U4D to follow. What is the purpose? Just using U4A is enough.

飞絮

Yes, the circuit can be optimized.