How to handle high di/dt load transients (Part 1)

For many central processing units (CPUs), the specification requires that the power supply must be able to provide large and fast charging output currents, especially when the processor changes operating modes. For example, in a 1V system, a 100 A/uS load transient may require the power supply voltage to be stabilized within 3%. The key to solving this problem is to realize that it is not just a power supply problem, the power distribution system is also an important factor, and it is difficult to strictly distinguish the two in a solution.

The implication of these high di/dt requirements is that the voltage source must have very low inductance. Rearranging the following equation and solving for the allowable source inductance gives:

The inductance during fast load current transients is only 0.3 nH. For comparison, a 0.1 inch (0.25 cm) wide board trace on a four-layer board has an inductance of about 0.7 nH/inch (0.3 nH/cm). The typical inductance of bond wires in IC packages is in the 1 nH range, and the inductance of printed circuit board vias is in the 0.2 nH range.

Additionally, there is a series inductance associated with the bypass capacitor, as shown in Figure 1. The top curve is the impedance of a 22 uF, X5R, 16V, 1210 ceramic capacitor mounted on a four-layer board. As we would expect (below 100 kHz), the impedance decreases with increasing frequency. However, there is a series inductance at 800 kHz, at which point the capacitor becomes inductive. This inductance (which can be calculated from the capacitor value and the resonant frequency) is 1.7 nH, which is much higher than our target value of 0.3 nH. Fortunately, you can use capacitors in parallel to reduce the effective ESL. The bottom curve in Figure 1 is the impedance of two capacitors in parallel. It is interesting that the resonance is slightly lower, indicating that the effective inductance is not exactly half. Based on the resonant frequency, the new inductance for the two capacitors in parallel is 1.0 nH or a 40% reduction in ESL, not a 50% reduction. This result can be attributed to two reasons: interconnect inductance and mutual inductance between the two capacitors.

Figure 1: Parallel capacitor impedance parasitic phenomenon attenuation effect

The size of the loop in the current path determines, to some extent, the parasitic inductance in the connected components, and the size of the component determines the area of ​​the loop. The size-to-inductance correlation coefficient is shown in Table 1, which shows the capacitor inductance of various sizes of ceramic surface mount capacitors. Generally speaking, larger capacitors have greater inductance. This table does not include the inductance of the capacitor mounted on the board, which increased from 1 nH to 1.7 nH in our previous measurements. Another interesting point is that the location of the termination has a great impact on the inductance. The 0805 capacitor has terminations on the shorter side of the capacitor while the 0508 capacitor has terminations on the longer side. This almost splits the current path in half, greatly reducing the inductance. This changed structure reduces the inductance by one quarter.

Table 1 Ceramic SMT capacitor size affects parasitic inductance

Dimensions ESL (nH)
0603 0.6
0805 0.8
0508 0.2
1206 1.0
0612 0.2
1210 1.0

In summary, high di/dt loads require careful consideration of bypassing to maintain dynamic regulation of the supply. Surface mount capacitors need to be very close to the load to minimize their interconnection inductance. Capacitors have parasitic inductance that can prevent a lot of decoupling. Shunt capacitors to reduce this parasitic inductance are effective, but interconnect and mutual inductance reduce this effect. Using capacitors with shorter current paths is also effective. This can be implemented with smaller parts or parts with AC terminations that use shorter dimensions for current.

Please join us next time when we discuss high di/dt transient loads and their implications when designing and testing power supplies. We will then shift the focus from local bypassing to power supply design implications.

For more information on this and other power solutions, visit www.ti.com/power.