A DDS frequency synthesizer with improved spurious

0 Introduction
Due to the wide application of frequency hopping technology in the military, the research on its core direct digital frequency synthesizer has become a hot topic. The basic principle of direct digital frequency synthesizer is to use the different phase differences of the input signal itself to give different voltage amplitudes, and finally filter and smooth the output of the required frequency. The biggest problem in designing a direct digital frequency synthesizer is spurious suppression. This is an important indicator for evaluating whether the frequency synthesizer design is good.
Spurious mainly consists of amplitude quantization spurious and phase truncation spurious. The technologies currently used to solve spurious are roughly divided into: modifying frequency control word technology, phase jitter technology, etc. Phase jitter technology can well improve the spurious caused by phase truncation, but it increases the bottom noise of spurious. The method of modifying the frequency control word can reduce the spurious by 4 dB overall, but it concentrates the scattered spurious on a certain frequency, causing the noise on this frequency to appear spikes. Here, we first use the method of correcting the frequency control word to reduce the overall spurious by about 4 dB, then use the phase jitter technology to improve the spurious caused by phase truncation, and finally use the delay superposition technology to delay the D/A conversion results to improve the bottom noise problem of the spurious and effectively suppress the side frequency. Finally, Matlab simulation is used to demonstrate the effectiveness of this comprehensive method, which improves both the spurious caused by amplitude quantization and the spurious caused by phase truncation.

l Basic principles of DDS frequency synthesizer
The basic DDS frequency synthesizer consists of a phase accumulator, a phase register, a sine lookup table, a DAC, and a low-pass filter. The adder register adds the digital signal from the binary register to the accumulator, and then changes the value of the phase register with the current value, so that the accumulator overflows periodically at each reference clock pulse input. When there is a new change in the frequency tuning word, the binary register provides the new phase increment to the adder at the next reference clock. The basic structure is shown in Figure 1.

So we can get:

After passing through the SINE lookup table, its expression is as follows:

GCD represents the maximum deviation value. Then we can directly derive the time-frequency domain relationship between input and output, as shown in formula (3):

Formula (3) is the ideal DDS frequency expression obtained by Fourier transforming the input, represented by f(ω).

From the result of equation (4), we can see that after adding phase truncation, the spurious signal appears at ω=kω1±nωc±ω0.

[page]2 Improved structure
The first method of improvement is to add a trigger to the accumulator. The advantage of this is that the superposition value of Fr after the accumulator can be kept as an odd number. From the spurious model, it can be analyzed that as long as (Fr, 2j-k) are mutually prime, the distribution of discrete jitter of the entire spectrum can be reduced. After verification, it is shown that its overall SNR is reduced, but these reduced values ​​will increase to a frequency. Therefore, a DAC delay module is added to smooth the sideband, so that the spurious originally added to a certain frequency can be reduced and the filter can be helped to smooth the waveform. After combining the above two methods, the experiment shows that the overall spurious phenomenon caused by amplitude quantization has been significantly improved. The improved structure is shown in Figure 2.

It can be seen that after the improvement, the trigger on the accumulator will add the value of the D flip-flop back to the lowest bit of the accumulator when each clock arrives. If the value of the previous D flip-flop is "0", then at this time, after the inverted output of the D flip-flop, the value of the flip-flop becomes "1", and the accumulator adds a "1" to the lowest bit on the original basis. The same is true when the value of a D flip-flop is "1". This causes the output value of the trigger to jump between "0" and "1", so that the specific value after accumulation becomes 2*Fr+1, that is, ψ(n)=2Fr+1, which ensures that the number after frequency tuning and superposition is an odd number, so it is coprime with 2j-k. The advantage of this is that (△ψ, 2j-k)=1, and the original calculation is:

The disadvantage of this is that although the spurious signals at a certain frequency are reduced, the overall SNR is reduced compared to the original, and the reduced spurious signals are superimposed on a certain frequency.
In order to solve this problem, the phase dithering technology is introduced to address the influence of phase truncation. The error sequence generated by truncation is also periodic, so for a certain output frequency, the discretization of the signal phase caused by sampling is also periodic. Therefore, a dithering technology is needed to break this periodicity. The method is to add a random integer to the phase accumulator before each phase accumulator overflows, so that the overflow of the accumulator is randomly advanced to destroy the periodicity of the phase overflow.
In addition, for the spurious signals generated by amplitude quantization, the delay superposition method is also used before the filter, which can suppress the sidebands outside the main frequency. It is mainly to add a trigger in the DAc module to save the result of the previous D/A conversion at each clock delay. From the following derivation results, it can be seen that this improves the SNR, which is due to its suppression of sideband spurious signals. The following is the superposition of the sine values ​​after two D/A conversions, where:

Signal-to-noise ratio before stacking:

It can be clearly seen here that the SNR has been improved, and the reason for this is that the superposition module suppresses the sidebands outside the main frequency.

[page] Then, phase jitter technology is added. From the simulation results, it can be seen that it reduces the noise peak at this discrete spectrum very well, as shown in Figure 5, but it increases the spurious bottom noise. After adding the delay superposition module, the sideband is well suppressed, as shown in Figure 6. Especially when the frequency is (0.7~1)*π(rad/sample), the bottom noise is significantly reduced. However, due to the addition of the clock delay module, the overall conversion time is delayed by half fclk.

4 Conclusion
This paper first discusses the basic principle of direct digital frequency synthesizer and its spurious generation principle, and then combines multiple methods to solve the spurious problem. A trigger controlled by the same clock is added after the accumulator. Since the value of the trigger jumps regularly between "0" and "1", the value of the original accumulator changes from 2Fr to 2Fr+1, thereby ensuring its mutual prime with 2j-k, reducing the spurious at the frequency of ω=kω1±nωc±ω0, and reducing the spurious of the entire system by 4 dB, but it superimposes the scattered noise on one frequency. In addition, after phase jitter, the spurious caused by phase truncation is well suppressed, but the bottom noise is also increased. Therefore, on this basis, a delay superposition module is added to the DAC. Through theoretical derivation, it is known that it improves the signal-to-noise ratio, suppresses the sideband spurious, and suppresses the bottom noise caused by phase jitter to a certain extent. Finally, the above conclusions are verified through Matlab simulation. However, due to the delay of half a clock cycle and the increase in the number of triggers and registers, the conversion rate of the output signal is slowed down, which in turn affects the frequency hopping speed and increases power consumption. These are the next steps that need to be improved.