Frequency Synthesis System Implemented by DDS+PLL Combination Solution

　　The frequency synthesis system implemented by the DDS+PLL combination can achieve high frequency resolution, fast conversion and a wide frequency range to meet the frequency requirements of various aspects. The basic idea of ​​the synthesizer is to use a low-frequency DDS to excite a PLL frequency multiplication system to achieve high frequency resolution, high conversion rate and a wide output frequency.

　　1. Phase-locked frequency multiplication scheme of DDS-excited PLL
　　
　　This scheme uses DDS output as the excitation signal PLL of PH frequency multiplication, and is designed into an N frequency multiplication loop, as shown in Figure 1. By using a high phase-locked frequency to increase the conversion speed of PLL, and using the high frequency resolution of DDS to ensure the frequency multiplication PLL, a higher frequency resolution (N△φ×js/2m, where M and fs are the number of bits and clock frequency of the phase accumulator of DDS, respectively) can be achieved. At the same time, the bandpass filtering performance of the PLL loop can suppress the out-of-band spurious of DDS. The advantages of this scheme are simple circuit structure, low cost, easy control, and easy integration. Since PLL is used for frequency multiplication, the phase noise and spurious components in the DDS output signal that fall within the loop noise bandwidth will be multiplied by 2010gN dB. Therefore, when using this scheme, if the loop bandwidth is large in order to ensure the frequency conversion time, the N value cannot be too large. Generally, N<10 is taken to ensure the noise performance of the system.
　　

　　2. PLL interpolation DDS combination scheme
　　
　　This combination scheme is shown in Figure 2. Its output frequency

      fREF≤BWDDS is required. In this scheme, since DDS has a very high frequency resolution, PLL can use a high phase detection frequency REF, thereby improving the frequency conversion time of PLL. Since the output of DDS is not multiplied by PLL, the phase noise and spurious output of DDS will not deteriorate at the output end, so this scheme has low phase noise and excellent spurious performance. Its disadvantage is that BPF design is difficult. Because the larger the OUT value, the closer the distance between fOUT-fDDS and fOUT+fDDS is, which requires BPF to have strict g rolling frequency characteristics. In order to solve this problem, the improved scheme shown in Figure 4 can be used. First, use the local oscillator fL to mix with DDS, and move the output of DDS to a relatively high frequency, which reduces the design difficulty of BPF. This scheme maintains the advantages of the scheme in Figure 3, but has an additional mixing link, which increases the hardware complexity and debugging difficulty, because mixing will bring certain parasitic components in the output.
　　
　　From the above analysis, it can be seen that the DDS excitation frequency multiplication PLL solution has the simplest circuit structure and uses the least hardware. When the output frequency band is certain, the output frequency of DDS can be increased as much as possible (using a high clock frequency DDS), thereby increasing the phase detection frequency of PLL. In this way, the frequency hopping speed can be increased and the frequency multiplication number N can be reduced to prevent serious deterioration of noise performance. Inexpensive CMOS process DDS products can output signals of more than ten MHz, and only a few times of frequency multiplication are required to reach the VHF band. At a phase detection frequency of 10 MHz, PLL can achieve a frequency hopping speed of tens of μs, so this solution is particularly suitable for frequency hopping frequency synthesizers in the VHF band or high-resolution frequency sources covering this band.