FPGA Implementation of Digital Up-Down Conversion for Multi-antenna and Multi-carrier

Digital up-conversion/down-conversion (DUC/DDC) is an important part of digital intermediate frequency design. Its function is to convert the baseband signal to the intermediate frequency after interpolation filtering, or to reduce the intermediate frequency signal to the baseband frequency after extraction filtering. The main purpose of this article is to introduce the FPGA implementation method of multi-antenna multi-carrier digital up-down conversion, as well as a digital signal processing tool provided by Altera, DSP BUILDER.

DUC/DDC implementation architecture Taking

TD-SCDMA's DUC/DDC as an example, with a baseband frequency of 1.28MHz, 4 antennas and 9 carriers, 60 times up-conversion, and 30 times down-conversion, the DUC architecture is shown in Figure 1

Figure 1, Architecture diagram of DUC.

First, there are 4 antennas and 9 carriers, each carrier is divided into two IQ channels, with a total of 4×9×2=72 channels. The data of these 72 channels are first combined into one channel by the duc_input_mux module and input into the duc_rrc_filter for 2x interpolation and root raised cosine filtering, which is a 121-order filter; the output result is divided into 4 channels and sent to 4 int5_filter (61-order) modules for 5x interpolation and compensation filtering; the output of these 4 filters is further divided into 24 channels and sent to the int6_filter (41-order) module for 6x interpolation and filtering; the result enters the mixer module mixer, mixed with the intermediate frequency signal generated by the NCO, and output as the final result.

Figure 2, DDC architecture

The architecture of DDC is shown in Figure 2. For DDC, the input is the data from 4 antennas, which are distinguished to different frequency points by the mixer, and then the decimation filter dec5_filter (41 order) performs 5-fold decimation and filtering; the result is compounded to 3 channels, and 3 decimation filters (61 order) perform 3-fold decimation and filtering; finally, ddc_rrc_filter (121 order) performs 2-fold decimation and filtering.

We can see that for DUC/DDC, the main modules are FIR filters, mixers, and numerically controlled oscillators NCO, and the multiplexing and demultiplexing logic occupies very little resources. The filter occupies most of the resources, including lookup tables, registers, RAM, and multipliers. Therefore, optimizing the filter design to save resources and using the smallest possible FPGA to achieve more channels of digital up and down conversion has become the main difficulty in implementation.

Introduction to DSP-BUILDER

DSP-BUILDER is a design tool of Altera Corporation. It can be regarded as a bridge between MATLAB SIMULINK and FPGA implementation software QUARTUS II. Simply put, in the SIMULINK environment, calling the library components provided by DSP-BUILDER, such a mathematical model system can be built, not only can it be simulated in MATLAB, but also can directly generate an ALTERA FPGA project, and then conduct hardware verification after comprehensive layout and routing. One point to emphasize here is that only by calling the library components in DSP-BUILDER can a comprehensive and implementable project be generated.

1. Versions after DSP-BUILDER8.0 provide a new ADVANCED BLOCK feature. The FIR filter generated by this new feature has made great improvements in resource optimization compared with previous versions.

2. Automatically insert pipeline. You only need to set the corresponding parameters, such as clock frequency, target device, reuse multiple, etc. It will automatically determine whether to join the PIPELINE while using as few resources as possible and meeting the timing.

3. System-level design. All modules it generates, including FIR filters, have a set of system interfaces, which can access internal registers, such as coefficients, through different addresses.

4. Automatic resource reuse. After the clock reuse relationship is determined, it can automatically realize resource reuse, freeing designers from tedious optimization work and focusing on system-level design.

Resources and power consumption of the entire design implemented by FPGA

This 4-antenna 9-carrier design is implemented on Altera Corporation's 3SE80F1152I3, with an operating frequency of 180 times the baseband rate clock, that is, 230MHz. The core static power consumption is 734.58mW, the core dynamic power consumption is 2705.63mW, the IO power consumption is 236.82mW, and the total power consumption is 3677.04mW.

3SE80 is one of ALTERA CORPORATION's 65nm products STRATIX III. This series of products takes many power optimization factors into consideration during the design process, so the power consumption characteristics are relatively good. For example, the core voltage is optional, which is 0.9V/1.1V. The above design uses a 1.1V voltage. If 0.9V is used, the power consumption can be reduced by another 30%. But there is one thing customers need to pay attention to. If 0.9V voltage is used, the timing of the entire design will be reduced by about 15%.