Principle and application circuit of MAX146/MAX147

1 MAX146/147 Overview

MAX146/MAX147 is a general-purpose A/D converter produced by MAXIM. It has 8 single-ended input channels or 4 differential input channels. It uses a single power supply, with the operating voltage of MAX146 being 2.7~3.6V and the operating voltage of MAX147 being 2.7~5.25V; MAX146 also has a 2.5V built-in reference voltage. They have low power consumption: the power supply current is 1.2mA at 3V/133kps, and only 1μA in power-down mode. In addition, it is compatible with SPI/QSPI/Microwire/TMS320 and has a 4-wire serial interface; the unipolar/bipolar input can be configured by software.

The pin arrangement of MAX146/147 is shown in Figure 1. It has two package types: 20-pin DIP/SSOP. The functions of the 20 pins of MAX147 are as follows:

Pins 1 to 8 (CH0 to CH7): analog signal input terminal;

Pin 9 (COM): reference ground for analog signal input;

Pin 10 (SHDN): three-state input terminal;

Pin 11 (VREF): reference buffer output/ADC reference input;

Pin 12 (REF ADJ): reference voltage input terminal;

Pin 13 (AGND): analog ground;

Pin 14 (DGND): data ground;

Pin 15 (DOUT): serial port data output;

Pin 16 (SSTRB): serial port rapid output;

Pin 17 (DIN): serial port data input;

Pin 18 (CS): low effective chip select signal;

Pin 19 (SCLK): serial clock input;

Pin 20 (VDD): 5V power input.

2 How the MAX146/147 Works

2.1 Definition of control bytes

The control byte of MAX146/147 consists of eight bits, bit7 to bit1, and their specific functions are listed in Table 1.

Table 1 MAX147 control byte definition

2.2 Conversion Start

When working, inputting the controlled byte to the DIN pin can start the conversion. When the CS pin is low, at each rising edge of SCLK, data is input from DIN to the internal conversion register of MAX146/147. After CS becomes low, the first logic "1" arriving on DIN is the MSB of the control byte, which starts the conversion signal. Before this, the "0" bit on DIN is invalid.

2.3 Software interface with CPU

Generally, the serial interface of the CPU should be operated in standard mode to ensure that the CPU generates a serial clock. The selected clock frequency should be between 100kHz and 2MHz. The software design steps are as follows:

(1) The format of setting the control byte TB1 to external clock mode is: 1xxxxx11B, where xxxxx is used to control the channel and conversion mode;

(2) Make the CPU use the general I/O line and make CS low;

(3) The CPU sends TB1 and receives a byte RB1 at the same time and discards it;

(4) Make the CPU send another byte (00h) and receive another byte RB2 at the same time;

(5) Let the CPU send another byte (00h) and receive another byte RB3 at the same time;

(6) CS is at high level.

Figure 2 shows the timing diagram of this process. Bytes RB2 and RB3 contain the result of the conversion, with the first and third bits being 0. The time of the entire conversion process is mainly determined by the clock frequency and the idle time between the two bytes. To avoid excessive attenuation of T/H, the total conversion time should be guaranteed to be no more than 120μs.

2.4 Data Output

In unipolar input mode, the output is an unsigned binary number; in bipolar mode, the output is a two's complement number, with data output on the falling edge of the clock, MSB first.

2.5 Clock Mode

MAX146/147 can use internal or external clock mode to perform continuous approximation conversion and drive each step of analog-to-digital conversion. When the last bit of the control byte is input, SSTRB rises one clock cycle and sends the converted continuous approximation bits to the pin at each falling edge of the 12 clock pulses. When CS is high, SSTFRB and DOUT are in high-impedance state, and SSTRB outputs a logic low level at the falling edge of CS. The entire conversion process must be completed within a few milliseconds, otherwise the conversion result will be attenuated by the sample-hold capacitor. When the serial clock frequency is lower than 100kHz, the internal clock mode should be used, otherwise the interval time will exceed 120μs.

3 Interface design with TMS320F206

The external clock mode interface circuit of TMS320F206 and MAX147 is shown in Figure 3. The following steps are required to start the conversion and transmit data through the serial port:

(1) Set the CLKK and CLKR pins of TMS320F206 and the SCLK pin of MAX147 to input state and rising edge valid, and both work in external clock mode.

(2) The XF pin of TMS320F206 outputs a low level to drive the pin of MAX147, so that MAX147 can receive the control byte from the DIN pin.

(3) Write a byte of the form 10001111 to the MAX146/147 so that the MAX147 can operate in single-ended, unipolar, external clock mode. 000 indicates that the first pin of the MAX146/147 is the analog signal input terminal.

(4) The output of the SSTRB pin of the MAX147 is used to provide an input signal to the FSR pin of the TMS320F206. The falling edge of SSTRB indicates that the conversion is in progress. The falling edge can also be used as a frame synchronization signal of the TMS320F206 to notify the TMS320F206 to prepare to receive data.

(5) At each falling edge of the next 16 clock signals, TMS320F206 will read out each data supplement bit of the conversion result, which has nothing to do with the conversion result and should be discarded.

(6) Change CS to a high level to put the MAX147 in a low power state until the next conversion is started, then change it to a low level.

4 Reference Wiring Method for MAX146/147

In order to make MAX46/147 work better, it is recommended to use a printed circuit board and try not to use enameled wire for connection. When wiring the printed circuit board, the data line and the analog circuit should be separated from each other. At the same time, it is forbidden to arrange the data line and the analog line in parallel, and the data line should not be passed under the MAX146/147.

Figure 4 shows the recommended wiring method. That is, connect all analog grounds to one point of the analog ground of the input end, connect all data grounds to one point, and then connect these two points. Other digital grounds cannot be connected to the starting endpoint of the analog input. To reduce noise on the ground line, the ground line at the input end should be as short as possible and the resistance should be as small as possible.

High-frequency interference on the power line will also affect the correct conversion of the A/D converter. For this reason, two capacitors with values ​​of 1μF and 0.1μF are connected in parallel between the power input pin VDD of MAX146/147 and the analog ground input starting point mentioned above in Figure 4. At the same time, the two pins of the capacitor should be as short as possible to reduce the interference introduced from the power supply. When the interference amplitude on the power supply is large, a 10Ω resistor can be connected between VDD and the power supply as shown in the figure to form a low-pass filter.