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w562601331
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Published on 2020-4-25 17:19
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This post is from ST MEMS Sensor Creative Design Competition
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Well, your analysis is correct. Chapter 4 of the document AN5273 specifically discusses the issue of FSM interrupts.
An interrupt is generated when the FSM reaches an end state or executes an OUTC/CONT/CONTREL command.
The interrupt will be stored in the interrupt status register address of the corresponding state machine module, which can be regarded as a soft interrupt from the perspective of master-slave device interaction.
By setting the INT1_FSM[1:16] and INT2_FSM[1:16] bits in the external interrupt INT configuration register, the external interrupt INT1/2 can be routed to the soft interrupt, thereby generating a hard interrupt.
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Published on 2020-4-26 10:27
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Published on 2020-4-26 10:27
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