Signal integrity analysis and simulation of high-speed PCB design based on Cadence_Allegro

Abstract: Signal integrity has become a major challenge in today's high-speed PCB design. Traditional design methods cannot achieve a high first-time design success rate. There is an urgent need for SI simulation-assisted design methods based on EDA software to solve this problem. This paper mainly studies the basic theories and solutions to common signal integrity problems such as reflection, crosstalk, and timing. Based on the IBIS model, the Spectraquest and Sigxp component tools of Cadence_Allegro software are used to simulate and analyze the SI of the designed high-speed 14-bit ADC/DAC application system, verifying the correctness of the solutions to common SI problems.
Keywords: high-speed PCB design; signal integrity; reflection; crosstalk; timing; SI analysis and simulation

0 Introduction
With the rapid development of semiconductor technology and people's demand for high-speed and broadband information, high-speed PCB design has become an important part of electronic product development. Signal integrity (SI) problems (including reflection, crosstalk, timing, etc.) have gradually developed into an unavoidable problem in high-speed PCB design. If the signal integrity design problem cannot be solved well, it may cause fatal errors in high-speed PCB design, waste financial and material resources, extend the development cycle, and reduce production efficiency.
The most mainstream high-speed PCB design today is based on SI simulation. Incorporating SI analysis and simulation into the design process to guide design optimization can better solve SI problems, and the first-time success rate of products is significantly improved compared with traditional design methods. At present, mainstream high-speed PCB design EDA tools such as Mentor's PADS and Cadence's Allegro SPB series support SI simulation and are powerful, providing favorable conditions for SI-based high-speed PCB design. For high-speed PCB designers, it is of great significance to be familiar with the basic theoretical knowledge of SI problems, master SI analysis and simulation methods, and flexibly design solutions to signal integrity problems.
This paper mainly studies the basic theories and solutions to common signal integrity problems such as reflection, crosstalk, and timing. Based on the IBIS model, the Specc-traquest and Sigxp component tools of Cadence_Allegro software are used to perform SI simulation and analysis on the designed high-speed 14-bit ADC/DAC application system example, verifying the correctness of the solutions to common SI problems.

1 Common signal integrity problems and solutions
1.1 Common signal integrity problems
Signal integrity refers to a state in which the signal is not damaged. It indicates the signal quality and the correct functional characteristics after the signal is transmitted. In a broad sense, it refers to all problems caused by interconnection in high-speed products, which affect the quality of high-speed signals in three forms: timing, noise, and electromagnetic interference (ENI). Common SI problems include reflection, crosstalk, delay, ringing, ground bounce, switching noise, power rebound, attenuation, etc. The key to solving signal integrity problems lies in the understanding of interconnect impedance. Many SI problems are related to interconnect impedance. The following will describe reflection, crosstalk, and timing problems from the perspective of interconnect impedance.
1.2 Reflection
Reflection problems reflect the signal quality of a single network and are related to the physical characteristics of the signal path and signal return path of a single network. When a signal propagates along a single network, it senses the transient impedance change of the interconnect line. If the interconnect impedance sensed by the signal remains unchanged, it remains undistorted; if the signal senses that the impedance of the interconnect changes, the signal is reflected at the change point, and distortion occurs. The main factors that cause changes in interconnect impedance include line width changes, layer conversion, return plane gaps, connectors, branch lines, T-type lines or stub lines, and network ends.
Signal reflection, overshoot, and ringing are all caused by impedance mutations. The amount of reflected signal is determined by the change in transient impedance. A single network is divided into pre-incident region 1 and post-incident region 2 by the mutation point. The transient impedances of the two regions are Z1 and Z2, respectively. The ratio of the reflected signal to the incident signal amplitude is:

Where: Vrefelect is the reflected voltage; Vincindent is the incident voltage; ρ is the reflection coefficient. It can be seen from formula (1) that if reflection is to be reduced, ρ needs to be reduced. The specific methods are: use controlled impedance interconnects; terminal matching at the end of the transmission line; use a wiring topology that is insensitive to multi-branch structures; and minimize transmission line geometric discontinuities. For point-to-point topologies, termination (i.e., controlling the impedance at one or both ends of the transmission line) is often used to reduce reflections. The main termination methods are shown in Figure 1.

As shown in Figure 1, the source end mainly adopts serial termination, and the far (load) end mainly adopts parallel termination, Thevenin termination, and RC termination. Due to the shortcomings of large current consumption of parallel termination, large DC power consumption of Thevenin termination, and low switching speed of RC termination, the most widely used method is the source end series resistance termination, which needs to be selected according to the actual design.

1.3 Crosstalk
Crosstalk occurs between two adjacent networks. If a network undergoes dynamic changes, it will couple noise to the adjacent static network through the action of the field, thereby affecting its signal quality. When the signal propagates, there is a fringe field between the signal path and the return path, which will produce capacitive coupling and inductive coupling, called mutual capacitance and mutual inductance. When a network undergoes dynamic changes, the capacitive and inductive coupling currents will affect the adjacent network through the action of the fringe field. Switching noise and ground bounce are both caused by crosstalk. Crosstalk is divided into near-end crosstalk (NEXT) and far-end crosstalk (FEXT), with the near end being close to the source and the far end being far away from the source. The amplitudes of NEXT and FEXT are as shown in equation (2) and equation (3) respectively:


Where: Vb is the backward noise voltage of the static line; Va1 is the signal voltage on the dynamic line; kb is the backward crosstalk coefficient; Vf is the far-end voltage of the static line; Va2 is the signal line voltage; k1 is the far-end coupling coefficient; is the length of the coupling area of ​​the two lines; RT is the rise time; CmL, CL, LmL, LL are the mutual capacitance, capacitance, mutual inductance, and inductance per unit length respectively. From equation (2) and equation (3), it can be seen that the main way to reduce NEXT is to reduce CmL and LmL, which can be achieved by increasing the distance between networks. The main way to reduce FEXT is to increase RT, reduce L, and increase the distance between networks. Reducing crosstalk will increase system cost, and a compromise is required to achieve the lowest cost while ensuring signal integrity.
1.4 Timing
Integrated circuits can only receive data according to the specified timing. Too long signal delay may cause timing violation and functional confusion. When the system clock is very high, the signal transmission time between devices and the synchronization preparation time are shortened. Drive overload and long routing will cause delays. High-speed circuits require that various gate delays be met in a very short time, including setup time, hold time, line delay, etc. Moreover, in high-speed PCBs, the distributed capacitance and distributed inductance on the transmission lines will cause delays in the digital switching of signals, affecting the setup and hold time of digital circuits. Excessive delays may cause the integrated circuit to be unable to correctly judge the data. Common timing systems are divided into two categories: ordinary timing systems and source synchronous timing systems. This article mainly introduces the timing issues of ordinary timing systems. The so-called common timing system (common clock timing system) means that the synchronous clock signals of the driver and the receiver are provided by a system clock generator. Its main restrictions are as shown in equations (4) and
(5):

Where: Ts,t, Th,t are the setup time and hold time respectively; Ts,m and Th.m are the setup time margin and hold time margin respectively; Tc is the clock cycle; Tp,s is the clock offset between two CLOCK traces; Tc.s is the offset between the two clock outputs of the clock driver (PLL); Tj is the error between the two clock cycles; Tc,d is the delay inside the driver; Tf,d is the flight time of the data line from the driver to the receiver. For any common clock control system, if it can ensure normal operation, the setup time margin and the hold time margin must be at least greater than zero, that is, Ts,m>T0,Th,m>0.

2 Simulation results and analysis based on Cadence_Allegro
2.1 Introduction to high-speed 14-bit ADC/DAC application system As
shown in Figure 2, this application system can be used for ADC/DAC chip verification. Based on the Cyclone2 series FPGA, it can realize DDC and DDS functions. In actual applications, the ADC to be tested uses Linear's 14-bit 105 MS/s chip LTC2284, and the DAC chip uses AD's 14-bit, 210 MSPS chip AD9783. The system PCB design is shown in Figure 2.

2.2 Reflection simulation and analysis of AD clock signal
The simulation is mainly based on the IBIS model, which is a model used to describe the characteristics of I/O buffer information. It can decompose the behavior description of an output and input port into a series of simple functional modules, and a complete IBIS model can be established from these simple functional modules. The clock of this application system is distributed to the ADC and DAC network through the clock buffer device after being multiplied by the FPGA software. The extracted topology from the FPGA phase-locked loop to the clock buffer chip is shown in Figure 3.
Its SI simulation is shown in Figure 4.

As shown in FIG4 , due to reasonable layout and routing, the high-frequency differential clock signal undergoes very little change when passing through the transmission line, thus maintaining good quality.

2.3 Simulation analysis of AD data signal
The SI simulation of the 0th bit of ADC channel A is shown in Figure 5.

As shown in Figure 6, the data waveform quality is significantly improved after using the termination resistor, and the termination can effectively solve the reflection problem caused by impedance mismatch.

3 Conclusion
The Spectraquest and Sigxp component tools in Cadence_Allegro software provide strong support for the design and simulation of high-speed PCB, including simulation model verification, topology analysis, pre- and post-routing simulation, constraint setting, PCB layout and routing and other hardware links. The simulation results can enable designers to better grasp signal integrity issues, optimize designs, improve the first-time success rate of high-speed PCB design, and better cope with the challenges faced by high-speed design.