Design of Data Communication Interface between PC104 Bus and DSP

After the birth of the first DSP chip in the world in 1982, after more than 20 years of development, the current DSP belongs to the fifth generation of DSP devices. Its system integration is higher, and the DSP core and peripheral devices have been integrated into a single chip. DSP has gradually become synonymous with digital signal processors. At the same time, digital signal processing technology has also made breakthrough progress in theory and algorithms, and it has also formed a relatively complete theoretical system, including data acquisition, discrete signal and discrete system analysis, signal estimation, signal modeling, signal processing algorithms, etc. DSP technology has been widely used in many fields such as aerospace, telemetry and remote sensing, biomedicine, automatic control, vibration engineering, communication radar, hydrological science, etc. It is an application mode in engineering to transmit raw data to DSP through the data acquisition system and complete the algorithm processing of DSP. The data transmission can be achieved through various computer buses.

PC104 is an industrial control bus specifically defined for embedded control. The main differences between PC104 and ordinary PC bus control systems are:

(1) Small size structure.

(2) Stack connection.

(3) Easy bus drive.

PC104 has two versions, 8-bit and 16-bit, corresponding to PC and PC/AT respectively. PC104 PLUS corresponds to PCI bus. This paper mainly deals with the design of 16-bit data communication interface between PC104 and DSP, using CYPRESS's dual-port static read-write memory CY7C028V15AC as shared memory. The right side of the dual-port RAM is connected to ADI's DSP chip TS101, and the left side is connected to PC104 bus. The control logic is implemented by EP1K100TC208 in ALTERA's ACEX series CPLD.

2Dual-port RAM access mode

CY7C028V15AC is a 16 b×64 k dual-port RAM that supports high-speed access with an access speed of 20 ns. It supports fully asynchronous access to the left and right ports. If the selection signals of the two ports are valid, both sides of the dual-port RAM can read and write to the dual-port RAM at the same time. What needs to be solved is the conflict problem when accessing a storage block at the same time. There are two ways to solve the access conflict: one is the signal token transfer method. The dual-port RAM provides 8 Semaphore latch units inside, which can logically divide the dual-port RAM into 8 segments; when a port wants to access a block, it first requests a token from the corresponding latch unit to determine whether the access will cause a conflict, that is, write "0" to a latch unit, and then read back the written data. If successful, the block corresponding to the latch unit is free and can be accessed, otherwise it cannot be accessed. When one side is accessing a block of the dual-port RAM, the corresponding latch unit cannot be accessed by the other side. The token application is implemented by reading and writing I/O. What is actually used are the D0 bit of the data bus on the left and right sides of the dual-port RAM, the A2~A0 bits of the address bus (whose decoding corresponds to 8 latch units), and the enable control terminals SEML and SEMR for accessing the latch units on the left and right sides. Another way is the interrupt mode. In the interrupt mode, the two highest addresses of the RAM are used as communication mailboxes, FFFEH is assigned to the right port, and FFFFH is assigned to the left port. The two mailboxes are used in the same way. Taking the right port as an example, when the DSP writes any value to the FFFEH address, the interrupt request signal INTL of the left port is valid. After responding to the interrupt request, the PC104 bus can clear the interrupt by reading the FFFEH address once.

In this paper, the handshake signal between PC104 and DSP is designed by interrupt mode . Considering the flexibility and reprogrammability of CPLD to design digital logic, CPLD is used to control interrupt request and response signals, so the two addresses at the top of RAM are still used as ordinary RAM units. The connection of the left and right ports of dual-port RAM is shown in Figure 1.

? When DSP requests data from PC104, TS101's flag FLAG0 is connected to one of PC104's interrupt signal pins through CPLD's buffer. When PC104 receives the interrupt request and finishes writing data to RAM, CPLD generates a reply signal to TS101's IRQ0 by writing to the I/O port. TS101 reads the data at the appropriate time and performs algorithm processing. When TS101 sends data to PC104, it first writes data to RAM. After writing, flag FLAG1 generates a read data request signal, which is connected to another interrupt signal pin of PC10 4 through CPLD buffer. PC104 responds to the interrupt and finishes reading data. CPLD generates a reply signal to TS101's IRQ1 by writing to the I/O port. When PC104 accesses dual-port RAM. The 16 bits of the data bus are connected to the I/O15L~I/O0L of the left port of the RAM through the CPLD buffer. Because the 16-bit data access occupies an even address, the A16~A1 of the address bus is connected to the A15L~A0L address lines of the left port of the RAM after the CPLD buffer. The remaining address lines of PC104 generate the selection signal of the left port of the RAM through the decoding in the CPLD. When TS101 accesses the RAM, the first 16 address lines of TS101 are connected to the A15R~A0R of the RAM, and the first 16 data lines are connected to the I/O15R~I/O0R of the right port of the RAM to generate the selection signal. Through the programming of TS 101, the effective address for accessing the RAM is defined by the user.

3PC104 and CPLD connection relationship

To access the dual-port RAM through CPLD, PC104 must first consider the storage address assigned to the RAM, because the 64 k×16 b RAM requires 64 k of even address space, or 128 k of continuous address space. The free address space available to users within 1 M of the industrial computer often does not reach 128 k. Therefore, the RAM should be arranged to be accessed outside the 1 M address space. At this time, in addition to the address lines SA19~SA0 used for 1 M addressing, the address lines LA23~LA17 for 1 M external addressing should also be used. It should be noted that SA19~SA17 and LA19~LA17 on the bus of PC104 are repeated. The difference is that SA10~SA0 is latched and output through the bus address latch enable signal BALE, while LA19~LA17 is not latched. In order to ensure that the address signal is always valid during the RAM access period, at least LA23~LA20 should be latched by BALE in the CPLD. In this paper, the RAM address is arranged at 64K even addresses starting from 100000H outside the 1M address space. All the PC104 signal lines needed are connected to the CPLD. The CPLD connects the SA16~SA1 buffer to the RAM, and the remaining address lines are decoded to generate the RAM left port selection signal. The access logic of the connection between PC104 and CPLD is shown in Figure 2.