How to Make DSP Digital Oscillator Generate Phase-Shifted Sine Wave

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How to Make DSP Digital Oscillator Generate Phase-Shifted Sine Wave [Copy link]

Introduction There are many ways to generate digital phase-shifted signals. The traditional direct digital frequency synthesis (DDS) phase-shifting principle is to first digitize the sine wave signal and form a data table to store it in two ROM chips. After that, the two D/A conversion chips can continuously output the data table in a loop under the control of the counter to obtain two sine wave signals. When the data sequences obtained by the two D/A conversion chips are exactly the same, the two sine wave signals obtained by the conversion have no phase difference. When the data sequences obtained by the two D/A conversion chips are different, the two sine wave signals obtained by the conversion have a phase difference. The value of the phase difference is related to the total number of data in the data table and the offset of the data address. The essence of this processing method is to map the offset of the data address to the phase value between the signals. The deviation of the data can be obtained by an external microprocessor to obtain the corresponding digital input, and this value corresponds to the phase shift angle of the sine signal. The direct frequency synthesis method has the advantages of short frequency conversion time, good phase noise performance, high accuracy, and a wide frequency range of the generated signal. However, due to the need to use address, phase calculation, memory access operations and other links, the direct frequency synthesizer has a complex structure, high cost, and low phase shift resolution. This paper uses DSP technology to obtain two sinusoidal signals through a numerical iteration method, that is, using the implementation principle of DSP digital oscillator. Through simulation and hardware implementation, two sinusoidal outputs with set parameters can be obtained, achieving the design purpose, and has the characteristics of convenient and flexible adjustment and high resolution. The numerical iteration method can accurately calculate the sine value of the angle, only requires a small storage space, selects the number of samples in the sine cycle, changes the delay between samples, and can generate waveforms of different frequencies. The waveform amplitude and phase can be changed by software. 1 DSP implementation principle of waveform and phase shift waveform generator Using DSP to generate sinusoidal signals through calculations, using the iterative method, that is, digital oscillator. The unit impulse response of the digital oscillator is sin(nωT+θ)·u(n), that is, the system oscillates under the excitation of δ(n), and outputs a sinusoidal sequence with a phase of θ. The system function of the system is the Z transform of the impulse response, that is,

When n≥3, we have: y(n)=2cosωT·y(n-1)-y(n-2). After n≥3, y(n) can be calculated using y(n-1) and y(n-2), which is a recursive difference equation. Therefore, the following conclusion is obtained: as long as the system output sinusoidal signal angular frequency ω and sampling period T are known, the system difference equation can be obtained. The system only needs to calculate the difference equation every T seconds to obtain the value of the current sinusoidal sampling sequence y(n). The initial phases are different when the initial values of y(1) and y(2) are set differently. In the design, the main program inputs data such as frequency and phase difference through the keyboard. During initialization, the initial values y1(1), y1(2) and y2(1)y2(2) of the two sinusoidal signals are calculated according to the output signal frequency, sampling rate and phase difference data, and then the timer interrupt is enabled. Each time the timer interrupt service program is entered, the new y1(0) and y2(0) are calculated using the previous y1(1), y1(2) and y2(1)y2(2). Although there is a certain delay in calculating and outputting y1(0) and y2(0) twice, the error caused will be very small due to the high-speed pipeline operation of the DSP and the high-speed serial output of the McBSP. 2 System Hardware Implementation Scheme The system structure of the two-way output phase-shifted sine wave based on the TMS320VC5416 DSP is shown in Figure 1. The central processing unit of the system uses the high-performance fixed-point digital signal processing chip TMS320VC5416 from TI (Texas Instruments) of the United States. TMS 320 VC54.16 is a low-power, high-performance fixed-point digital signal processor designed by TI specifically for portable devices. Compared with other processors in the C54 series, the running speed reaches 160MPIS, the on-chip RAM reaches 128K, and the program addressable space reaches 8M, which provides rich conditions for large-scale data processing. In particular, VC5416 provides a variety of on-chip peripheral resources; software programmable wait state generator, programmable phase-locked loop clock generator, 1 16-bit timer, 6-channel direct memory access controller (DMA), 3 multi-channel buffered serial ports (McBSP), 8-bit enhanced HPI interface, etc. In addition, TMS320VC5416 supports mixed programming of C and assembly languages. The efficient pipeline operation and flexible addressing mode make it particularly suitable for high-speed real-time signal processing. Since the system has two sinusoidal signal outputs, the system adopts two-way signal time-sharing transmission. TLC320AD50C is an analog interface chip produced by TI that integrates A/D and D/A conversion functions. It uses ∑-△ technology to achieve high-precision A/D and D/A conversion at low system cost. The chip consists of a pair of 16 b synchronous serial conversion channels, with a decimation filter after the ADC and an interpolation filter before the DAC. TLC320AD50C supports both master and slave working modes and supports up to three slave devices. Using this feature, the system connects two TLC320AD50Cs in series, making one the master device and the other the slave device, and realizes serial communication with the two TLC320AD50Cs through the multi-channel buffered serial port McBSP of TMS320VC5416. TMS320VC54.16 controls the two TLC320AD50Cs to transmit data to the two TLC320AD50Cs in a time-division multiplexing manner for D/A conversion output. The M/S of AD50C1 is connected to a high level, the M/S of AD50C2 is connected to a low level, and the XF pin of VC5416 is used to provide the primary and secondary communication selection signals for AD50C. TLC320AD50 is widely used in audio data acquisition and processing. It can be seamlessly connected to the McBSP of TMS320C54xDSP for data acquisition, storage and processing. SCLK outputs the clock, DIN serial input, DOUT serial output, and FS frame synchronization signal output, corresponding to the corresponding pins of DSP. MCBSP has the following characteristics: ① The receiving and sending clocks of the serial port can be provided by external devices or by internal clock generators; ② The polarity of the frame synchronization signal and the data clock signal can be programmed, and the internal clock and frame signal generator can also be controlled by software programming; ③ The signal sending and receiving parts of the serial port can run independently or work together; ④ The interrupt signal of the CPU and the synchronization signal of DMA enable the McBSP serial port to be controlled by the CPU, and can also be separated from the CPU and run independently through DMA to directly access the memory; ⑤ The multi-channel selection part enables the serial port to have the communication capability of multi-channel signals, and its multi-channel receiving and sending capabilities can reach 128 channels; ⑥ The data width can be selected from 8b, 12b, 16b, 20b, 24b, and 32b, and the data can be compressed and expanded by A law and U law. The McBSP serial port includes a data channel and a control channel. The data channel completes the sending and receiving of data. McBSP sends data through the DX pin and receives data through the DR pin. The tasks completed by the control channel include the generation of internal clocks, the generation of frame synchronization signals, the control of these signals, and the selection of multiple channels. The control channel is also responsible for generating interrupt signals to the CPU and generating synchronization event signals to notify the DMA controller. Control information is transmitted through the control channel in the form of clock and frame synchronization signals.The system software is mainly composed of several modules such as BootLoader download program, system initialization, keyboard display, and timer interrupt processing. When the system starts to power on, the BootLoader program is first executed to load the target program from the external FLASH into the on-chip RAM for execution. The system initialization program completes the initialization settings of the TMS320VC5416 control registers, McBSP serial port control registers, timers, and TLC320AD50C corresponding registers. The main program and timer interrupt service program flow chart are shown in Figure 2.

The CCS simulation waveform with a sine wave frequency of 2 kHz, a sampling frequency of 40 kHz, and a phase shift of 60 degrees is shown in Figure 3.

4 Conclusion This paper proposes a design method for generating phase-shifted sine waves based on DSP digital oscillator. The experimental results show that the waveform generated by the system is stable, has strong anti-interference ability, is easy to adjust the frequency, phase and amplitude, has high precision, the output frequency range is 20 Hz to 20 kHz, the phase shift is 0 to 360°, and the phase shift resolution can be as high as 0.001 degrees. In addition, if the system is connected to a high-speed DA conversion chip, the output frequency range can be greatly improved. This design is simple, feasible, novel and practical, and has the value of promotion and application.