Custom digital layout for next-generation chip designs

Layouts for large digital integrated circuit (IC) designs are typically created using highly automated place and route ( APR ) tools. Although there is much debate about using APR instead of custom layout, for most designs the speed and control advantages of APR outweigh the area or performance tradeoffs; however, designs that require the highest performance or the smallest area still rely on "hand" custom IC layout methods.

In the new generation of custom chips, complex rules, tight time-to-market schedules, and slim size and design complexity make the design of the entire custom digital block increasingly difficult to achieve. The fully automated APR flow cannot provide the necessary interactive control of layout and routing. Designers need a highly automated and controllable full-custom digital IC design flow to achieve the best performance, speed, and area.

This article details how the digital IC design team at a large fabless semiconductor company in the consumer products market leveraged standardized tool interoperability to maintain the advantages of manual layout for large, performance-critical 40nm designs. The team has effectively integrated tools from multiple vendors through the OpenAccess (OA) interoperability standardization effort of the Silicon Integra TI on Initiative (Si2), resulting in a more productive custom IC layout flow.

The benefits of controlled automation in custom designs

When designing mass storage solutions, design teams have for years deployed custom IC layout automation for their analog and custom digital designs. While analog designers have always used custom design methodologies, digital design teams typically turn to custom design tools and flows only when performance, power, speed, or area requirements exceed the capabilities of APR tools.

To achieve optimal performance and turnaround time, engineers use tools that use advanced controllable automation technology to create custom digital designs faster and with less effort. This includes an advanced schematic-driven layout (SDL) flow that uses highly configurable, process-independent parametric cell technology and device-level floorplan tools to provide the speed and control required to achieve optimal performance and density without changing design style or sacrificing quality of results.

Engineers automatically generate flight lines using connections inherited from the schematic, then manually route critical nets using a built-in rule-guided interactive router to meet demanding clock speeds exceeding 2GHz. At this level of performance, the routing of individual nets is sensitive to the environment and to interactions with other routes, nets, and even layers. To balance these elements, the design team must interact with all elements of the design environment. When manually routing, the design team can arrange routes, extract and evaluate critical nets for optimal timing, and then modify them until the desired value is achieved.

Figure 1. Flying lines show links and guide rule-guided manual routing

Meeting the challenges of next-generation custom digital design

Although custom layout and hand-routing methods can meet performance requirements, it is becoming increasingly difficult to complete new generations of custom digital blocks in a reasonable period of time.

As designs become larger and more complex, layout designers encounter severe routing issues and find themselves designing routing paths in uncharted territory, having to give up density to properly manage manual and point-to-point automated routing operations in increasingly larger blocks. While design teams can still achieve energy efficiency goals, they often pay the price of increased area, which is unacceptable in a cost-sensitive market. In addition, the time required to complete a design is far greater than that required for a single layout.

Figure 2. Interoperability in OpenAccess

As design teams move to 40nm processes to meet increasing performance demands, challenges are increasing. Blocks are becoming too large (too many interconnects) and design rules are too advanced for hand routing and existing automated custom routing solutions. No mass custom router can provide the deep submicron DRC-clean and DFM-aware routing technology required for advanced processes.

Initially, the design team attempted to use a hybrid flow, using the layout editor to manually route critical nets as before, and then using APR’s digital router with advanced DRC rules to complete noncritical nets. Unfortunately, the constant switching between multiple tools reduced productivity. No matter how efficient the individual steps were, the custom and digital design domains were not closely aligned. In addition, the approach was not interactive, causing the team to lose hierarchy and connectivity data. The automated router would often re-route some of the carefully drawn critical nets, requiring extensive manual proofreading and even reworking the router. As a result, the design team would spend six weeks iterating to achieve acceptable, but not optimal, results.

Figure 3. The winder identifies obstacles and winds the wire.

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Even on non-critical nets, automated routing can improve the productivity of design teams as long as it does not hinder the ability to iterate. Moreover, the precise spacing constraints required by some pre-routed and guided APR tools are not currently present. As a result, undesirable parasitic effects in custom modules are instead caused, requiring labor-intensive manual rerouting and multiple lengthy re-executions.

While automation generally improves productivity, it currently makes difficult processes more tedious because designers have no control over the results. In fact, manual proofreading of critical nets in a fully routed layout often takes more time than manually routing them from scratch. The design team concluded that in order to achieve the best results in less time, a heterogeneous environment that maintains hierarchy, connectivity, and design integrity through controlled automation is required.

Interoperability saves time

The standards organization Silicon Integration Initiative (Si2) provides an interoperable database for electronic design automation (EDA) tools called OpenAccess (OA), which has become a standard for custom designs in recent years. A little-known feature of OA is the OA Run Time Model (OA-RTM), which can be executed on OA as an in-memory model for EDA tools. This means that completely different tools can operate on the same memory agent of design data at the same time. Using OA-RTM, tools from multiple vendors can work together as smoothly as tools from a single vendor.

Using OA-RTM, Pyxis Technology's new high-performance custom router operates within the Laker custom layout environment. This high-capacity custom digital router has been customer-proven to create DRC-correct, DFM-aware routes at 45nm and below; it can perform routing at all levels and is incremental, meaning that existing critical nets that were manually created do not need to be changed. When running the custom IC layout system, the designer can select the chip area and have the integrated router perform routing for all nets within that constraint. Ports that force specific routing paths as well as blockages, changes and fixes, and existing routes are all recognized by the router, with no data conversion or storage to disk required.

Figure 4. Interactive environment enables what-if analysis

With this interoperable solution, design teams can create layouts the same way they did before, using automated custom IC layout systems and SDL methodologies. Routing of transistor layers is performed by the layout tool, as are critical nets. Alternatively, pre-wires that define routing of critical nets can be defined by the layout editor. Routing is performed in stages, starting with critical nets and then executing ordered groups (hierarchical), or entire blocks, all in a matter of minutes.

Design teams can also take advantage of the custom router’s built-in extraction and timing engines to quickly feedback parasitic parameters and sample timing. This allows engineers to determine when the routing topology is “good enough” to avoid over-routing. Moreover, the speed and controllability of this custom flow is very useful for quickly evaluating the placement of layout elements to achieve the best results. The router can also add “dummy fill” (redundant metal, usually inserted into the layout to increase data density, achieve uniformity and flatness) to help identify possible destructive parasitic effects to ensure that the dummy fill set by the wafer factory does not cause unexpected problems.

Combining these capabilities with a highly automated custom layout system, the design team worked with the EDA vendor to create a solution that can perform rapid, iterative "what-if" analysis while optimizing layout and routing. With the ability to iteratively route, extract, analyze timing, modify and verify, the design team was able to reduce the design costs required to achieve higher performance goals while also reducing power and area – all in a fraction of the time previously required for a single layout.

Test Results

Specific testing involving a critical, high-performance block previously required six weeks to achieve an acceptable solution. The performance requirements of this block conflicted with the area and power requirements, making it very difficult to achieve a complete success. To confirm the performance of the router, the existing routing was removed. The design was flattened in the layout editor and the entire block was automatically routed in a few minutes. Mimicking the standard flow, additional versions were quickly generated in which the critical nets were routed manually using the layout editor, and the remaining nets were implemented using the automated router. No critical nets were changed during the automated routing process, and no DRC violations were encountered.

After the initial proof of concept, the design team demonstrated consistent results, and large, high-performance custom digital blocks that would normally take three to six weeks to build can now be built in just one week. This means that the design team can free up more time to optimize the performance, area, and power consumption of the custom blocks, ultimately achieving higher value in the product.