Design of Phase-Shifted Clock Frequency Measurement Module

According to the characteristics of rapid frequency changes of radar transmitters, this paper uses the current new logic control device to study a new frequency measurement module, combines the principle of equal-precision interpolation frequency measurement, directly counts the pulses after shaping and amplification, and realizes the rapid frequency measurement of the carrier of the single pulse envelope after down-conversion. It has the characteristics of high measurement accuracy and short measurement time, and can be used as a single pulse instantaneous frequency measurement module for pulse radar.

1 Frequency measurement principle of phase-shifted clock counting method

The phase-shifted clock counting method is based on the equal-precision frequency measurement method and is a new interpolation technology. Its multiple clocks with the same frequency but different phases are generated by the PLL inside the FPGA, and then transmitted to the corresponding counters for counting. During the actual gate opening period, each counter counts simultaneously; after the actual gate is closed, the total value is used for frequency measurement. The specific method is: the actual gate is used as a key logic signal, connected to the count enable end (cnt_ena) of the four synchronous counters through the global clock wiring, as the count enable signal of the counter; the four clock signals are used as the counting clocks of the counters, and are connected to the clock ends (clk) of the four counters respectively, so that the four counters count the actual gate pulse width, and the counters are set to count by 1 on the rising edge of the clock. Assume that the count values ​​of the four counters are ns1, ns2, ns3, and ns4, and the total value is N's. Since the change of each counter count value will cause the value of N's to change, and the count clocks corresponding to n21, ns2, ns3, and ns4 have a 90° phase difference (Tdk/4 count time), the count value N's will increase by 1 every Tdk/4 time. This is equivalent to quadrupling the frequency of a standard count clock. After a measurement is completed (i.e., the actual gate is closed), the formula is used to calculate the actual gate pulse width measurement value, and the equal-precision frequency measurement formula is:

Comparing equations (1) and (2), we can see that the result of the sum operation of the four counter count values ​​ns1, ns2, ns3, and ns4 is used as the new count value for frequency measurement, and the frequency measurement result is equivalent to quadrupling the standard frequency. This conclusion can also be explained from the perspective of relative error. Since the actual gate and the measured signal of the equal-precision frequency measurement method are synchronized, there is no quantization error in Nx in equation (2). However, if the actual gate and the standard clock are not synchronized, N′s will have a ±1 quantization error. The relative error of the frequency measurement is:

Since the count value N′s is almost 4 times of Ns, the error corresponding to equation (2) is 1/4 of that corresponding to equation (1). That is, by using the method of measuring the frequency with four phase-shifted clocks, the relative error of the measurement is reduced to 1/4 of the original error while the measurement time and the reference clock frequency remain unchanged, and the measurement accuracy is improved by 4 times. If the number of phase-shifted clocks is increased, the measurement accuracy will be further improved.

2 Overall design of the new frequency measurement module

The intermediate frequency instantaneous measurement module is constructed by using the phase-shifted clock counting method to realize the frequency measurement. The measurement object of this frequency measurement module is the intermediate frequency signal after the pulse radar receiver is down-converted. The overall design goal is to build a digital, integrated, and automated test platform that can meet the requirements of intra-pulse frequency measurement, can perform remote communication, and has a certain degree of transplantability and upgradeability. The basic framework of the system is shown in Figure 1.

The working mechanism of the whole system is: the operator sets the parameters and selects the functions of the module through the upper computer human-machine interface. The setting values ​​of the human-machine interface are transmitted to the single-chip microcomputer through the serial port. The single-chip microcomputer, as the control component of the measurement module, controls the FPGA to complete the corresponding measurement task. The FPGA is responsible for the specific frequency measurement algorithm implementation. After the test is completed, the test results are transmitted to the upper computer human-machine interface through the single-chip microcomputer for display. The two are connected through the RS232 serial port. The frequency measurement algorithm circuit inside the FPGA is the core circuit in the whole design.

3 FPGA frequency measurement algorithm circuit design

The StratixII series EP2S15F484C5 FPGA of Altera is used as the core control unit. The internal frequency measurement algorithm circuit mainly includes the routing of the PLL output clock, the timing control unit, and the data processing unit. These units are the core of the frequency measurement algorithm. Each unit needs to be connected inside the FPGA according to the interface provided by each other to form a complete frequency measurement module and realize the equal-precision frequency measurement function. The input signals are a 10 MHz clock signal, a pulse envelope signal, and a measured signal; the output signals are the clock count value and the ns measured signal count value nx. The overall principle block diagram is shown in Figure 2.

By using PLL to output multiple counting clocks, the maximum multiplication number can be increased by cascading PLLs inside the FPGA. First, use EPLL to multiply the 10 MHz clock input by the constant temperature crystal oscillator to 50 MHz and transmit it to FPLL as the reference clock of FPLL. FPLL then multiplies the input clock to 400 MHz, and phase shifts and taps to obtain four phase-shifted clocks. The FPLL phase shift degree is set to: 0°, 90.0°, 180°, 270.0°, and the actual degree is consistent with the set value. Since 4 global clock lines are arranged around FPLL, all the output clocks of FPLL can be routed through the global clock line through the GLOBAL device. [page]

The measured signal is a carrier signal of a pulse modulated wave. After being processed by a shaping amplifier circuit, the signal forms a pulse train and is input into the dedicated clock pin of the FPGA. Due to the influence of the circuit and the device, the amplitude and frequency of the head and tail signals of the pulse train are unstable, which is manifested as a large frequency fluctuation inside the FPGA. Therefore, only the stable part in the middle of the pulse train can be selected as the measurement object.

The pulse envelope signal is provided by the detection circuit as the pulse width input signal of the measured signal. If the variable gate frequency measurement method is adopted, the pulse width counter measures the width of each pulse envelope, and its pulse width value is saved at the falling edge of the pulse envelope, and is provided to the pre-gate counter as the pre-gate count reference value before the rising edge of the next pulse envelope.

The frequency measurement scheme requires a 1 ms gate time measurement for the continuous wave. For a 400 MHz standard clock signal, a 20-bit synchronous counter is used to count the measured signal and the standard clock. The counting frequency of the 20-bit synchronous counter can reach 416 MHz, and its maximum count value is 1048576. When counting with a 400 MHz standard clock signal, the corresponding counting time is 2.6 ms. The counter is automatically generated by calling the IP core provided by ALTERA using the Mega Wizard Plug-in Manager toolkit in Quartus6.0 software.

4 Peripheral circuit design

The peripheral circuits include a constant temperature crystal oscillator circuit that provides a standard 10 MHz clock for the FPGA; a shaping circuit that amplifies and shapes the input signal; a pulse envelope detection circuit; and a power supply circuit that provides -5 V, +1.2 V, +3.3 V, and +5 V voltages for the entire module.

The frequency measurement accuracy requirement for this project is ±10-6, and the frequency accuracy of the oscillator must reach at least ±10-7. Only a voltage-controlled constant temperature crystal oscillator can be used to build a standard frequency source. The crystal oscillator used in this project is a product of Chengdu Xinghua Company. Through the Allan variance test software inside the instrument, the second stability of the OCXO is 3.3×10-12, and the short stability of 100 s is 4.4×10-12.

The amplitude of the measured signal transmitted by the signal receiver is usually only in the millivolt level, while the input port of the FPGA is generally LVTTL level, so the input signal needs to be level converted. The maximum frequency of the LVTTL level format input port of the FPGA reaches 200 MHz. In order to match this frequency value and avoid forming a speed bottleneck, the ultra-high-speed ECL level output comparator ADC-MP563 is used to complete the signal shaping function, and the level converter MC100EPT25 is connected in series to complete the conversion from differential ECL level to LVTTL logic level.

The pulse envelope detection circuit detects the envelope of the measured signal and is used to measure the pulse width. The detection circuit is constructed using the AD8310 detection chip from AD Company, and the detection of the measured signal adopts a single-ended input method. The host computer uses CV18.0 to build the human-machine interface.

5. Simulation Results

Test method: Use the output signals of Agilent's vector signal generator E4438C and arbitrary waveform generator 33250 as the measured objects, and use the frequency measurement module to measure the signal frequency. Each count value is uploaded to the host computer processing software through the microcontroller serial port. The software implements the algorithm of formula (2) through the program to calculate the measured frequency value. The measurement results are shown in Table 1.

Table 1 shows the measurement of carrier frequency within an indefinite pulse width. The gate time is determined based on the measured pulse width of the first pulse envelope after the measurement begins. Since the E4438C has large fluctuations when generating a 4μs pulse width, the actual gate time deviation is large at certain frequencies. The experiment shows that the system measures the frequency of the pulse modulated wave carrier, and the measurement accuracy of the intermediate frequency is better than ±10 kHz under the condition of indefinite pulse width (about 4μs).

Table 2 shows the measurement of carrier frequency in an indefinite pulse width. The frequency source is Agilent's arbitrary waveform generator 33250. The experiment shows that the system can measure the frequency of the pulse modulated wave carrier with an accuracy better than ±30 kHz for the intermediate frequency in an indefinite pulse width (≤400 ns).

6 Conclusion

The equal-precision instantaneous frequency measurement module based on multi-channel phase-shifted clocks proposed in this paper has the characteristics of simple circuit and high cost performance, and can be used for intra-pulse frequency measurement of agile frequency pulse modulation radar. The core frequency measurement circuit is completely built inside the FPGA, and the input standard clock is only 10 MHz, which not only reduces the difficulty of wiring and board making, but also greatly improves the module's anti-interference ability and ensures measurement accuracy. The entire frequency measurement module is implemented with a board card, and the expected effect is achieved through testing, proving that the design scheme is highly practical.