High-speed transient signal detection system based on FPGA and DSP

introduction

At present, there is an urgent need for a method and means to monitor the firing process of electric pyrotechnics in real time without loss, and to make accurate judgments and certifications on the reliability of pyrotechnics based on the monitoring results, so as to solve specific problems in scientific research and production. This system uses an induction coil as a non-contact ignition current initiation device, and uses advanced integrated circuits such as high-speed A/D, FPGA, and DSP to achieve lossless detection of electric pyrotechnics. Its main purpose is: first, to solve the detection, processing and storage technology of microsecond transient signals in the reliability test of electric pyrotechnics; second, to provide an online lossless real-time detection system for reliability testing, so as to monitor the entire ignition process of electric pyrotechnics; third, to provide a real evaluation basis for the certification and evaluation of the ignition reliability of electric pyrotechnics, reduce or eliminate the economic risks caused by rejecting products, and at the same time reduce or eliminate the hidden dangers in the quality of weapons and equipment caused by incorrectly accepting products.

1 System composition

The composition of the entire system is shown in Figure 1. When the detonation circuit is detonated under the control of DSP and FPGA, the induction coil extracts the detonation current. The first is the high-speed data acquisition and storage circuit, which uses FPGA as the core to collect and store data at high speed. After the data is stored, FPGA sends a signal to inform DSP that the collection is complete and starts to process the collected data. The content of DSP's signal processing: first filter the signal, then perform necessary time domain and frequency domain analysis, and extract relevant signal characteristics.

The processed data is transmitted to the computer through the USB port, and then professional related analysis is performed. If a high-speed DSP is used for data acquisition here, it is a waste of the computing power of the DSP. In terms of high-speed data acquisition, FPGA has advantages that microcontrollers and DSPs cannot match. FPGA has a high clock frequency and a small internal delay; all control logic is completed by hardware, which is fast and efficient. Therefore, the system shown in Figure 1 is formed.

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2 Hardware Circuit

2.1 High-speed data acquisition and storage circuit

In order to monitor the detonation current of electric ignition devices with an action time of μs in real time, a high-speed data acquisition and storage circuit composed of some large-scale integrated circuit chips is used, as shown in Figure 2.

The main content of the non-loss detection of electric ignition products is the measurement of the detonation current.

The action time of the detonation current of the electric ignition device is in the μs level. XCS30 is an FPGA chip based on SRAM technology of Xilinx. It issues instructions to charge the capacitor Cl and detonate the electric ignition device DT. The non-contact induction coil is used as a detection device for the detonation current to extract the voltage. The front-end conditioning circuit is to expand the amplitude range of the measurable signal, set up an amplifier, and amplify the small signal to ensure sufficient dynamic range; secondly, in order not to affect the measured signal, the input end should have a higher input impedance. The voltage measured in the experiment has noise, so the noise is filtered out through a filter. However, after this treatment, the driving ability of the signal decreases, so that the A/D cannot sample correctly, so a follower is added to enhance the driving ability, so that the A/D can sample correctly.

The main tasks of XCS30 are: ④ Control the conduction of thyristor D1 to charge capacitor C1; ② Control the conduction of thyristor D2 to start the electric pyrotechnics; ③ Start A/D conversion at the same time as D2 is turned on to achieve synchronization between A/D sampling and the detonation signal; ④ Generate address signals to store the data output by A/D in SRAM; ⑤ Determine whether the storage space of SRAM is full to end A/D sampling, and output CLKR signal to notify the data processing and transmission circuit shown in Figure 3 to read the data in SRAM. Among them, tasks ① and ② are performed under the control of DSP, as shown in Figure 3, that is, XCS30 can complete the above two tasks only after receiving the instructions of DSP. The reason why DSP controls D1 and D2 to conduct through XCS30 is to improve the driving ability of the load. In other words, the driving ability of XCS30 is stronger than that of DSP, and it can reliably turn on thyristors D1 and D2.

In actual use, the main performances achieved by the data acquisition and storage circuit are: ① the sampling rate reaches 40 Msps, that is, the sampling interval is 25 ns; ② the memory capacity is 512KB; ③ the maximum duration of the sampled signal is 12.8 ms.

The duration of the sampled signal varies from μs to ms due to the different detection objects, so the sampling frequency cannot be fixed. After analysis, the minimum sampling frequency is 5 MHz and the maximum sampling frequency is 40 MHz. The frequency of the FPGA external crystal oscillator is 40 MHz, so it should be divided by 8. A two-position toggle switch is connected externally, and the corresponding sampling frequency is 40 MHz when "00" and 5 MHz when "11". [page]

2.2 Data processing and transmission circuit

TMS320VC33 is the core device of the circuit shown in Figure 3. Its main functions are: ① Read the data of the SRAM shown in Figure 2. The connection relationship in the circuit is that A19 of TMS320VC33 selects the output enable signal OE of AS7C34096A, and the address lines A0~A18 and data lines DO~D7 of DSP are connected to Ao~A18 and data lines D0~D7 of SRAM respectively. ② Process the read data, including necessary time domain and frequency domain analysis, mainly FFT of large data volume. ③ Transmit the collected and processed data to the computer through the serial interface chip.

DS1270 is a non-volatile memory. Its output voltage high level is 5 V, but the I/O port level of TMS320VC33 is 3.3 V, which cannot withstand the TTL signal with a high level of 5 V. In order to enable TMS320VC33 and DS1270 to exchange data, 74LVC4245 is used to achieve 3.3V and 5V level conversion. 74LVC4245 has both 3.3V and 5V power supplies. The I/O pin connected to DSP has a level of 3.3V, and the I/O pin connected to DS1270 has a level of 5V.

Since the TMS320VC33 chip has a ROM, the program and data information will be lost after power failure, so an external memory is required. Here, the Flash chip AM29F040 is selected to store the program, and the DS1270 is used to store the data during and after the data processing process. The power chip TPS767D318 generates 3.3V and 1.8V voltages to power the DSP; after power-on, the reset pin of the TPS767D318 will generate a low level, and this signal will reset the DSP at the same time. The DSP will guide the program from the program memory to the high-speed RAM area and then start to execute at full speed. The data enters the DSP, and the DSP processes the data, that is, it performs the necessary time domain and frequency domain analysis, extracts the relevant signal features, and puts the processed results back into the DSl270. [page]

3 Software Design

The core device of the circuit shown in Figure 2 is XCS30. The above five functions are implemented by VHDL. The process is shown in Figure 4(a). In the figure, CHG and FIR are sent to XCS30 to charge capacitor Cl and start the ignition device DT; ENCODE is the signal to start A/D conversion; WR is the signal to write SRAM, and the address value A=7FFFFh indicates that SRAM is full. At this time, XCS30 outputs CLKR signal, indicating that the sampling and storage process has ended.

Figure 4(a) is divided into four functional modules: generating firing signal, frequency divider, frequency selector, and address distributor. Figure 4(b) is the DSP program flow.

Write a VHDL program and simulate the waveform in ISE7.1 as shown in Figure 5.

4 Summary

The advantages of DSP include: strong data processing capability, high-speed operation, real-time complex calculations, single-cycle multi-function instructions, and abundant serial port resources. By taking advantage of DSP's powerful data processing capability and high operating speed, the accuracy and real-time performance of the analysis system can be improved to meet the higher performance requirements of the monitoring system. Since high-tech chips such as DSP and FPGA are applied to the system, one chip can realize many functions, thus reducing the use of other devices and streamlining the motherboard system; in particular, it is convenient to add functions, and only the software needs to be modified. In this way, the cost of the entire system is relatively reduced, and the performance of the entire system is enhanced.