Research and design of low power storage tester based on XCR3256

This paper introduces the modular design of a storage tester based on XCR3256, and uses XCR3256 as the main control unit to implement data collection, editing, storage and retransmission technology. In view of the traditional method of reducing power consumption mainly through hardware circuits, this paper proposes a specific low-power technology that combines software and hardware. It analyzes the impact of software operation on XCR3256 and system power consumption, introduces several effective methods to achieve low power consumption, and gives some test data.

0 Introduction

In the scientific research process of various aircraft systems, there are usually two ways to test dynamic data: one is radio telemetry, and the other is to use a dedicated transmission line to detect the working status of the aircraft. However, when the flight system re-enters the atmospheric plasma interruption zone or is underwater, it is impossible to obtain system status information in a timely and dynamic manner. The storage tester, i.e., the black box [1], can collect various status information of the aircraft in real time in harsh environments such as the above, and store the collected data in a certain data format, and reproduce the working status of the aircraft in the blind area afterwards. The storage tester provides an important basis for the establishment and analysis of fault models in the above test process.

With the continuous development of science and technology, components are integrating more functions. In addition to intelligence, large storage capacity, safety and reliability, the requirements for testing equipment miniaturization and low power consumption continue to grow. The realization of low power consumption goals must be implemented in all aspects from the development of electronic devices to the design of terminal products.

1 System design and working principle

The storage tester is an organic whole, and it also exchanges information with the system under test. Therefore, its various related systems must match, be compatible, and work in coordination with each other. Timing matching, impedance matching, accuracy matching, dynamic range matching, etc. are achieved in the modular design.

1.1 System Design

The data storage tester is based on the XCR3256 master control, which can realize the functions of collection, editing, storage and retransmission. It can collect various types of signals through the interface module under the control of instructions, and store the collected data in a 32×32 frame format under the frame and code synchronization signal instructions after data processing. The system block diagram is shown in Figure 1.

Based on the diversity of aircraft signal forms, the input interface design includes analog input, 422 differential serial digital input and parallel digital input. The data processing for the above input data includes optical isolation processing and serial-to-parallel conversion of serial data, sampling and A/D conversion of analog quantity, and finally generating parallel data, which are written into the memory respectively under the control of the central control module. The data processing unit is shown in Figure 2.

When the system is powered off, the data can be retained previously due to the low-power data retention module. The data retention capability can be up to one year. When the system is powered on again, the data can be read out through the parallel port, differential serial port or high-speed USB port.

Figure 1 Data storage tester structure diagram

Figure 2 Data processing unit[page]

1.2 Working Principle

The system's working states mainly include data acquisition state, data storage state, data retransmission state, and low-power data retention state. The data storage state is parallel to the data acquisition state, and the retransmission state can be performed by interrupting the storage state during data storage, or by judging the frame count to complete the full retransmission. A special word header is added before the retransmission data to mark the start of the retransmission cycle. It can also be retransmitted directly after power-on, and all retransmissions can be cyclically retransmitted.

Figure 3 Data storage and retransmission workflow diagram

Data storage framing implementation method: Start the data storage state by issuing a storage command. There are two frame synchronization signals, corresponding to the last two frame identifiers EB,90 of each main frame. The main frame includes three counts, namely low count, medium count and high count. The low count determines the length of the sub-frame. When the low count counts from 00 to 1F (hexadecimal, the same below), the low count is cleared and the medium count is carried. At the same time, the frame identifier of the main frame is rewritten from EB,90 to 14,6F (corresponding to the sub-frame synchronization signal at this time), thereby realizing the 32×32 full-frame data format. When the medium count counts to FF, the high count is cleared and carried. Whether the data record is missing or wrong can be identified by judging whether the frame count is continuous.

The data format of each sub-frame is arranged as follows: when the low count is 00, 01, the frame header is inserted, when the count reaches 1E, 1F, the current middle count and high count are recorded, and the middle 28 frames record the working status parameters of the system. The same position in the full frame is the status of the same parameter at different times. [page]

2 Methods for achieving low power consumption

Traditional means of reducing system power consumption are mainly focused on hardware, such as: selecting low-power devices, arranging different power supply circuits, etc. However, hardware is only a platform, and the role of software cannot be ignored. Almost every chip access and every signal flip on the bus are controlled by software. If the software can reduce the number of external memory accesses and respond to interrupts in a timely manner, it will make a great contribution to reducing power consumption.

2.1 Hardware

2.1.1 Chip-level low power consumption implementation technology

In this design, most devices such as main control chip, memory, bus driver, FIFO, etc. are CMOS and HMOS low-power devices.

The main control chip is Xilinx's CPLD, model XCR3256, 3.3V operating voltage, low power operation, 5V and 3.3V compatible I/O ports. All unused I/O ports are set to output (no external drive signal). If the I/O is suspended, a little interference from the outside may become a repeatedly oscillating input signal, and the power consumption of CMOS devices basically depends on the number of flips of the gate circuit. In addition, since the suspended input pin is in the transition zone between 0 and 1, the P channel and N channel of the inverter in the circuit can be turned on, which will also increase the power consumption of the CPLD itself. If they are pulled up, each pin will also have a microampere current. Therefore, all different I/Os are set to output in the design.

2.1.2 Circuit-level low power implementation technology

Formula (1) is the calculation formula for the power consumption of CMOS circuits [3]. Where: P is the total static and dynamic power consumption; m is the number of nodes; n is the total number of devices; VDD is the operating voltage; fak is the clock frequency; ILn is the reverse leakage current; ISCn is the transient short-circuit current; am is the node charging rate; cm is the node capacitance.

From this formula, it can be seen that lowering the system operating voltage can achieve the purpose of reducing system power consumption. The central control module is powered by a dedicated low-voltage power supply module TPS70358. TPS70358 can provide two power supply modes of 3.3V/2.5V, and it also has power management function.

Figure 4 is a low-power data retention circuit. When the system is powered, the battery can be charged. When the system is powered off, the battery can power the memory to achieve self-retention of data. The static power consumption of the memory is only 10mW. It can be calculated that the data retention period achieved by this circuit can reach more than one year.

Figure 4 Low power data retention circuit [page]

2.2 Software

As we know, for programmable logic devices, the number of internal trigger flip-flops and the output of the switch have a great impact on the power consumption of the device itself. This design implements the power consumption adjustment of the main control chip itself through software, and achieves system-level low power consumption by controlling the chip enable and bus working status in the system.

2.2.1 Using state machine encoding

State machine coding is used in the main program to assign protection to input and output signals. For input signals that do not need to be updated in the final output signal, state machine control is used to prevent them from propagating to the next state or other logic blocks. The output value is changed only when necessary, reducing unnecessary switch outputs.

Figure 5 82C52 state machine configuration module and simulation results

The data coming out of the data acquisition and processing module and entering the data storage module are actually three-way data. Through the state machine and latches, the three-way data occupy the data bus of the memory at different times, effectively suppressing invalid switching activities.

2.2.2 Make full use of the enable control of components

During the operation of the entire system, sometimes the behavior of some devices is not necessary for the current function, but it increases unnecessary power consumption. For example, when the chip select is valid, the power consumption of the memory will be more than dozens of times greater than when the chip select is invalid, regardless of the state of the read and write signals. In this system, by mapping a control system to the central control module, the chip select and enable of each chip and control logic are shortened as much as possible while meeting the necessary constraints. By removing the use of devices that are not related to the current operation, the total switching activity of the system is effectively reduced, reducing the power consumption of the system. [page]

2.2.3 Using gated clock technology

The whole program is divided into several parts, including the debouncing module, the configuration module of 82C52, the address generator module, the parallel-to-serial conversion module and the data framing module, which include several processes. The clock of the module that is not used temporarily is stopped. Because the reduction in the number of active clock buffers directly leads to a reduction in the number of flip-flops, the possible reversal of the flip-flop output is also reduced. The use of gated clock technology requires careful planning and segmentation algorithms, which can save considerable system power consumption.

The BUFE in the 82C52 configuration module in Figure 5(a) can achieve the gating function.

In addition, the higher the system clock frequency, the more frequent the clock signal switching activity, the greater the capacitive load, and the greater the system power consumption. Therefore, the system clock also has a significant impact on the system power consumption. Combined with the actual situation, a 9.8306MHz crystal oscillator is selected in this design.

3 Conclusion

The technical indicators of the data storage tester are as follows:

◆Data storage capacity 2MByte;

◆30 data storage channels;

◆80-channel analog sampling;

◆422 differential serial digital sampling;

◆Parallel digital quantity acquisition;

◆System power consumption: 50mA;

The relevant technology has been applied to the testing of a certain project, storing and retransmitting the system's digital and analog quantities during movement, and achieved good results.

The application of this technology has expanded to various fields. It not only provides an economical and efficient means for obtaining important parameters of aircraft, but also provides sufficient basis for fault analysis of ground, water and underwater vehicles such as aircraft, automobiles, tanks, ships and submarines. It is of certain significance to continuously improve various types of vehicles and reduce their development and maintenance costs.