To build a signal chain, you need to know the high-speed signal knowledge (1)

Why use LVDS or JESD204B standards?

The signal chain is the bridge between the real world and the digital world. With the improvement of ADC sampling rate and sampling accuracy, the signal transmission speed of interface chips is getting faster and faster, and various challenges of high-speed signal transmission slowly emerge. As a signal chain design or verification engineer, you must know these basic concepts.

Compared with traditional CMOS transmission technology, introducing LVDS or JESD204B into the signal chain can achieve higher signal transmission rates, lower power consumption, better anti-interference (better signal-to-noise ratio), and the number of wire harnesses will be significantly reduced.

LVDS (Low-Voltage Differential Signaling) is a level standard for signal transmission mode proposed by National Semiconductor (NS, now TI) in 1994. It uses extremely low voltage swing transmission High-speed differential data can realize point-to-point or point-to-multipoint connections. It has the advantages of low power consumption, low bit error rate, and low crosstalk. It has been widely used in various occasions of serial high-speed data communication. The most well-known ones are notebook computers. LCD display, high-speed digital signal transmission of data converter (ADC/DAC), video stream transmission of automotive electronics, etc.

JESD204 is a high-speed serial interface developed by the standardization organization JEDEC for data transmission between data converters (ADC and DAC) and logic devices (FGPA). JESD204 uses CML (Current-Mode Logic) technology to transmit signals. Revision B of the standard supports serial data rates up to 12.5 Gbps and ensures repeatable deterministic latency for JESD204 links. As converter speeds and resolutions continue to increase, and FPGA chips increasingly support the JESD204B standard, JESD204 is becoming more common in high-speed converters and integrated RF transceiver applications.

Figure 1: Comparison of various low-level buses

LVDS is a current-driven high-speed signal that applies a 3.5mA constant current source at the transmitting end. By controlling the switching tube on and off, the current flowing from the transmitting end to the receiving end can continuously change between the forward and reverse directions, thereby achieving a differential voltage change of +/-350mV on the 100 ohm differential load at the receiving end. The maximum can be achieved 3.125Gbps high-speed data transmission. LVDS uses differential line transmission, which will bring several significant advantages:

a. Allow common mode voltage differences between the transmitter and the receiver (within the range of 0-2.4V)

b. Excellent anti-interference ability and excellent signal-to-noise ratio

c. Extremely low voltage swing and extremely low power consumption

Figure 2: How LVDS works

Traditional LVDS uses a synchronous clock method, using a pair of differential clocks to provide clock reference for up to three pairs of data signals. In each clock cycle, each pair of data transmits 7 bits of information. A SerDes chip is needed to convert the parallel signal into a high-speed serial signal through parallel/serial conversion when sending; when receiving a high-speed serial signal, use serial/parallel conversion to restore the parallel signal.

Figure 3: LVDS synchronization clock provides reference for data

The LVDS used now also supports 8b/10b SerDes to achieve more efficient signal transmission. This transmission method no longer needs to use a clock signal, but only needs to transmit the Data signal, saving a pair of differential lines. Through 8b/10b encoding, 8-bit valid data is mapped into 10-bit encoded data. Although this process increases the overhead by 25%, it can ensure that there are enough frequent signal transitions in the data. After receiving the signal, the clock is recovered from the data through a phase-locked loop (PLL). This transmission architecture is called embedded clock (Embeded Clock). 8b/10b encoding can also achieve DC Balance for the transmitted signal, that is, the number of 1s and the number of 0s are basically maintained equal. DC balanced transmission links can be connected in series with DC blocking capacitors to improve the noise and jitter performance of the link. Embedded clocks and 8b/10b are widely used in industrial high-speed transmission standards, such as PCIe, SATA, USB3, etc., including JESD204 (CML).

Figure 4: How the LVDS embedded clock works (image source TI)

Different from LVDS, CML (Current-Mode Logic) uses a voltage drive method to apply a constant voltage Vcc on the source end. By controlling the switching tube on and off, the receiving end can obtain a changing differential voltage. CML uses an embedded clock and 8b/10b encoding, with a higher operating voltage than LVDS. It also uses equalization technology in the sending and receiving chips to ensure an excellent bit error rate during high-speed, long-distance transmission. JESD204B using CML technology can support data rates up to 12.5Gbps, and its latest C version can even support data rates up to 32Gbps.

Figure 5: CML signal transmission method

So when we design high-speed interface chips, should we use LVDS or CML (JESD204)? The simple principle is that CML has higher speed, while LVDS consumes less power.

Figure 6: Selection of LVDS and CML

When the Data Rate is lower than 2Gbps, LVDS is more widely used, with lower power consumption, strong anti-interference, and a wide common-mode voltage range that makes interconnection requirements very low. LVDS also has M-LVDS and B-LVDS standards that support multi-point interconnection, which can interconnect multiple nodes and have many application scenarios. When the data rate is higher than 3.125Gbps, CML must be used. When the data rate is between 2G and 3.125Gbps, the balance of functionality, performance, and power consumption must be considered comprehensively. For example, when the transmission distance is long but the signal quality requirements are very high, consider using CML; when the transmission distance is short and long battery life and low power consumption are required, consider using LVDS.