Basic test techniques for memory and digital chip testing

Introduction to memory chip testing

A memory chip is a chip used to store digital information under specific conditions. The stored information can be operation codes, data files or a combination of the two. According to different characteristics, memories can be divided into the following categories, as shown in Table 1:

Definition of memory terms

Before discussing memory chip testing, it is necessary to define some related terms.

Write Recovery Time: The time a storage unit must wait between a write operation and a correct read.

Hold Time: The time interval during which the input data level must be maintained after the latch clock.

Pause Test: Test of memory content retention time.

Refresh Time: The maximum time interval for memory refresh.

Setup Time: The time interval during which the input data level must remain stable before the clock is latched.

Rise and Fall Times: Functional speed testing is done by repeatedly performing functional tests while changing the cycle or frequency of chip testing. Test cycles are often changed using binary searches. These tests measure the chip's fastest operating speed.

Write Recovery: The time that a storage unit must wait between a write operation and before the next storage unit can be read correctly.

Read time (Access time): Usually refers to the minimum time required from read enable, chip select signal or address change to outputting new data at the output end. The read time depends on the memory read process.

Functional testing in memory chip testing

Memory chips must undergo many necessary tests to ensure they function correctly. These tests are primarily used to ensure that the chip does not contain the following types of errors:

Storage unit short circuit: storage unit is connected to the power supply or ground circuit.

Open circuit of memory cell: The state of the memory cell cannot be changed when writing. Short circuit of adjacent cells: According to different short circuit states, adjacent cells will be written with the same or opposite data address.

Open circuit or short circuit: This error causes one memory cell to correspond to multiple addresses or multiple addresses to correspond to one memory cell. This error is not easy to detect because we can only check the output response corresponding to the input address at a time, and it is difficult to determine which physical address was actually read.

Storage unit interference: It means that when writing or reading a storage unit, it may cause the state of its surrounding or adjacent storage cells to change, that is, the state is disturbed.

Test vectors used for error detection during memory chip testing

The test vector is a series of functions applied to the memory chip, that is, different combinations of functions such as reading and writing. It is mainly used to test the functional errors of the chip. Commonly used memory test vectors are as follows, and their execution methods and test purposes are introduced respectively.

All "0" and all "1" vectors: 4n row vector execution method: write "1" to all cells and then read and verify all cells. Write "0" to all cells and then read to verify all cells.

Purpose: Check for short circuit or open circuit errors in the storage unit. Short circuit problems in adjacent units can also be checked.

Checkerboard vector: 4n row vector

Execution method: First run the 0-1 checkerboard vector, that is, write 1 in the first unit, write 0 in the second unit, and then write 1 in the third unit, and so on, until the last unit, and then read and verify all units. Then run a 1-0 checkerboard vector, which means writing the exact opposite data to the 0-1 checkerboard to all units, and then reading and verifying all units.

Purpose: This is the most basic and simple test vector for functional testing, address decoding and unit interference. It can also check for consecutive address errors or interference errors, and is often used as a vector in time measurement.

Patterns Marching vector: 5n row vector

Execution method: first write 0 to all units, read the first unit, and then write 1 to the first unit. Read the second cell, write 1 to the second cell, and so on until the last cell. Finally, repeat the above operation, but write the data in reverse.

Purpose: This is the most basic and simple test vector for functional testing, address decoding and unit interference. It can also check for consecutive address errors or interference errors, and is often used as a vector in time measurement.

Walking vector: 2n^2 row vector

Execution method: first write 0 to all units, and then read all units. Next, write 1 to the first unit, read all units, and write the first unit back to 0 after reading. Then write 1 to the second unit, read all units, and write back 0 to the second unit after reading. And so on, repeating until the last unit. After the above operation is completed, repeat the above operation, except that the data written is reversed.

Purpose: Check all address decoding errors. Its disadvantage is that it takes too long to run. Assuming that the read and write cycle is 500ns, the wakling vector test on a 4K RAM requires 16 seconds of test time. If we know the memory structure, we can only walk rows or columns to reduce test time.

Galloping write recovery vector: 12^2n row vector

Execution method: Write 0 to all units. Then write 1 to the first cell (the base cell), read the second cell, and then go back and read the first cell. Then write 0 to the second unit and read the second unit. Then repeat this operation between all other units and the base unit. After the operation of the first unit as a basic unit is completed, use the second unit as a basic unit and perform the same operation again. And so on until all units have been treated as base units. Finally, repeat the above process again, but write the data in reverse.

Purpose: This is an excellent vector for functional testing, address decoding testing and interference testing. It also works well for write recovery testing if proper timing is chosen. It also works well for read time testing.

Other test vectors are similar to these vectors and are based on the same core concept.

Dynamic Random Read Memory (DRAM)

The testing of dynamic random access memory (DRAM) has the following special requirements:

1. Row address and column address are input on the same address line (column address multiplexing). They are latched through RAS and CAS signals respectively.

2. The chip needs to be refreshed within a fixed time interval.

3.DRAM can perform page operations. Therefore it is necessary to keep the row address the same and change the column address (or vice versa).

Introduction to logic testing

Logic chip functional testing is used to ensure that the device under test can correctly complete its expected functions. In order to achieve this goal, a test vector or truth table must first be created before errors in the test device can be detected. There is a unified criterion for the ability of a truth table to detect errors, called fault coverage. Test vectors and test sequences combine to form the core of logical function testing.

test vector

Test vectors—also called test patterns or truth tables—consist of input and output states that represent the logical functionality of the device under test. Input and output status are represented by characters. Usually 1/0 is used to indicate input status, L/H/Z is used to indicate output status, and X is used to indicate the status of no input and no comparison of output. Virtually any set of characters can be used to represent a truth table, as long as the test system can correctly interpret and perform the corresponding function of each character.

Test vectors are stored in vector memory, with each row of individual vectors representing the "raw" data for a single test cycle. The data input from the vector memory is combined with timing, waveform format and voltage data and applied to the device under test through the pin electronIC circuit. The output of the device under test is compared with the data stored in the vector memory at the appropriate sampling time through the comparison circuit on the pin electronic. This type of testing is called stored response.

In addition to the input and output data of the device under test, the test vector may also contain some operating instructions of the test system. For example, it is necessary to include timing information, etc., because the timing or waveform format may need to be switched in real time between cycles. Input drivers may need to be turned on or off, and output comparators may need to be selectively switched between cycles. Many test systems also support micro-operation instructions like jumps, loops, vector repeats, subroutines, etc. Different testers may express tester instructions differently, which is one of the reasons why vector conversion is required when transferring the test program from one test platform to another.

For more complex chips, the test vectors are generally extracted from simulation data during the chip design process. The simulation data needs to be reorganized to meet the format of the target test system, and some processing needs to be done to ensure correct operation. Generally speaking, test vectors are not simply composed of millions of rows of independent vectors. Test vectors or simulation data can be completed by design engineers, test engineers or verification engineers, but to ensure successful vector generation, a very comprehensive understanding of the chip itself and the test system is required.

Test resource consumption

When developing a functional test, all aspects of the device under test's performance and functionality must be considered. The following parameters should be tested or set carefully:

VDD Min/Max (power supply voltage of the device under test)

VIL/VIH (input voltage)

VOL/VOH (output voltage)

IOL/IOH (output current load)

VREF (IOL/IOH conversion level)

Test frequency (cycle used for testing)

Input signal timing (clock/setup time/hold time/control)