PCIe 5.0 product testing and verification is in full swing, ready to lead the consumer market in the future

Electro Rent provides PCIe 5.0 development customers with a flexible budget and fast delivery test solution

Ensuring sufficient bandwidth and power supply for the PCIe bus has become a constant goal. The demand for higher speeds has driven standard organizations to define the next generation of PCI Express. The speed of PCIe 5.0 has doubled from 16GT/s of PCIe 4.0 to 32 GT/s. With the newly released PCIe 6.0, the bandwidth rate has doubled across the board, and PCIe 6.0 has made improvements to the underlying signaling.

Keysight Technologies has just released a complete test solution for PCIe 5.0/6.0, which enables it to provide a full range of physical layer test solutions, becoming the only company that currently provides complete test solutions from modeling, simulation, interconnect parameter characterization, Tx, PLL and Rx. Through the joint support of Keysight Technologies' leasing partner Electro Rent, customers can find the latest products at a fraction of the purchase price of test instruments and get them at the fastest speed. In recent interactions with customers who need PCIe 5.0 test solutions, we deeply feel the urgent needs of customers and their satisfaction with our services, and work together to help customers gain future market opportunities.

Evolution to the Next Generation PCIe Standard

PCI Express 5.0 represents the latest PCI standard using non-return-to-zero (NRZ) signaling, doubling the speed from 16GT/s in PCIe 4.0 to 32 GT/s. The PCIe 5.0 standard was completed in 2019. In response to the growing demand for high-performance computing, artificial intelligence accelerators, high-performance storage, etc., PCI-SIG has begun to develop the next-generation PCIe 6.0 specification. The PCIe 6.0 v1.0 version specification was officially released in January 2022.

PCIe 6.0 has ultra-low latency, ultra-high bandwidth, and ultra-fast speed. In addition, PCIe 6.0 has improved the underlying signaling, which is also the biggest improvement in the history of PCIe. By doubling the PCIe link speed, PCIe 6.0 has actually doubled the bandwidth rate. The x1 channel has increased from 4GB/s to 8GB/s, and the x16 channel has been expanded to 128GB/s in one direction and 256GB/s in two directions. This means that the device can use fewer channels to achieve a higher rate, thereby achieving the effect of reducing hardware costs.

Although the PCIe 6.0 standards have been released, it is undeniable that from the perspective of the consumer market, the PCIe 5.0 market is still in its early stages. Most consumers are still stuck at PCIe 4.0, mainly because the prices of products that support PCIe 5.0 are very high. For consumers, PCIe 4.0 does not affect the work and gaming experience, so the penetration rate of PCIe 5.0 is still relatively low. However, the testing and verification of PCIe 5.0 related products is in full swing.

Next-Generation PCIe 5.0 Testing Challenges

PCIe 5.0 testing challenges increase as the speed doubles, and the biggest challenge comes from channel length. The faster the signal speed, the higher the signal carrier frequency transmitted on the PC board. There are two types of physical damage that limit the expected distance that engineers can transmit PCIe signals: one is channel attenuation, and the other is reflections that occur within the channel due to impedance discontinuities found in pins, connectors, through-holes, and other structures.

The PCIe 5.0 specification uses a channel with an attenuation of -36 dB at 16 GHz , which represents the Nyquist frequency for a 32 GT/s digital signal . For example, when a PCIe 5.0 signal starts, it may have a typical peak-to-peak voltage of 800 mV. However, after passing through the recommended -36 dB channel, nothing resembling what it would look like with open eyes is found. Only by applying transmitter-based equalization (de-emphasis) and receiver equalization (a combination of CTLE and DFE) can a PCIe 5.0 signal pass through the system channel and be accurately interpreted by the receiver.

For PCIe 5.0 signals, the minimum expectation for eye height is 10 mV (after equalization). Even with a near-perfect low-jitter transmitter, significant attenuation in the channel can reduce the signal amplitude to the point where any other type of signal impairment caused by reflections and crosstalk can close the recoverable eye.

To help ensure the success of products supporting PCIe 5.0, Keysight Technologies is actively providing test solutions. Based on physical layer system simulation, physical layer interconnection, and transmitter (Tx) and receiver (Rx) tests, the latest PCIE5.0 protocol analysis test solution has been added, which can now provide testing and verification from design simulation to physical layer and then to protocol layer.

UXR+M8040 PCIe 5.0 test upgrade platform

Keysight Technologies' UXR0334A+M8040A realizes the upgrade of PCIe 5.0 high-speed interface test platform, which is also a recent hot demand of Electro-Lite customers.

After the signal enters the oscilloscope, it passes through the analog front end including attenuators, amplifiers, and samplers, and then enters the ADC. Differences in the semiconductor process, packaging design, interconnection design, and vertical effective bit number of the ADC used in the oscilloscope will lead to differences in the signal-to-noise ratio. Therefore, reducing the instrument noise floor and increasing the number of ADC bits will greatly help improve measurement accuracy. Under the condition of sufficient sampling rate, these performances exceed the impact of using a higher sampling rate on the measurement results.

Figure 1 Oscilloscope front-end signal acquisition link

Based on the InP HB2C process MMIC front-end, multi-chip 3D packaging interconnection and 10-bit ADC, the UXR series oscilloscopes have significantly higher margins in terms of eye height, eye width, TJ and other results under 1e-12 conditions of PCIe 5.0. Taking the 33GHz bandwidth UXR0334A oscilloscope as an example, under the same vertical full-scale conditions, the noise floor index of UXR is half the level of the 33GHz bandwidth oscilloscopes of the same industry.

In addition, from the measurement method, the vertical scale setting will affect the measured signal-to-noise ratio. One important point during measurement is to optimize the vertical scale and let the signal fill the vertical full scale as much as possible, so as to achieve the best measurement signal-to-noise ratio. As can be seen from the table below, under the same test conditions: using the M8040A bit error tester, adding a certain amount of pressure, a 36dB loss built by the PCIe 5.0 Base fixture, setting the same Preset P9, using the same receiving CTLE DC Gain 10dB, the oscilloscope has optimized the vertical scale.

The M8040A high-performance BERT is a highly integrated bit error rate tester (BERT). The M8040A is designed for R&D and test engineers to help them characterize chips, devices, transceiver modules and subassemblies, circuit boards, and systems. It can not only test PCIe 5.0, but also explore the development path for the emerging PCIe 6.0 technology. It is suitable for physical layer characterization and compliance testing. It supports PAM4 and NRZ signals, as well as data rates up to 64 GBaud, covering all the features of the 400 GbE standard.

As a leasing partner of Keysight Technologies, Electro Rent provides customers with greater value and flexibility in leasing services and test asset management in the face of many uncertainties and complex and changing industry situations, and makes continuous efforts to better serve customers.