Oscilloscope Series: DDR Memory - Overview, Development Cycle and Challenges

DDR Memory Overview

Memory is everywhere now—not only in servers, workstations, and desktops, but also embedded in consumer electronics, automobiles, and other system designs. Each generation of DDR SDRAM (double data rate synchronous dynamic random access memory) has been accompanied by faster speeds, smaller packages, and lower power consumption (see Table 1). These improvements in features have also brought designers more challenges in reducing design margins, improving signal integrity, and interoperability.

DDR Memory Interface

The Joint Electron Devices Engineering Council (JEDEC) has now introduced a new DDR standard for low-power DDR (LPDDR) or mobile devices (Mobile DDR). As the name implies, this standard uses lower signal amplitudes, further improving power consumption. Currently, the standard has reached the technical specifications of DDR1. Engineers will not need to redesign the link layer or protocol layer of the device to enjoy the benefits of reduced power consumption, because the voltage level of the system can be adjusted with little investment.

Table 1. JEDEC defines the DDR specification, but it leaves compliance to the designer or adopter rather than enforcing it.

The DDR memory interface transmits control, address, clock, strobe, and data signals. As shown in Figure 1, the clock, address, and control signals are transmitted unidirectionally from the memory controller to the DDR chip; the strobe and data signals are transmitted bidirectionally. In a read operation, the strobe and data signals are transmitted from the DDR chip to the memory controller. In a write operation, the signals are transmitted in the opposite direction.

As data transmission rates increase and signal amplitudes decrease, in order to improve signal performance, clock and strobe signals use differential signals, which can eliminate common-mode noise. Other signals are still operated in single-ended mode and are more susceptible to noise, crosstalk, and interference.

Figure 1. In a DDR interface, clock, address, and control signals travel from the memory controller to the DDR chip, while strobe and data signals travel in both directions. Their direction depends on the operation to be performed.

Common DDR Verification Challenges

Figure 2. The basic activities in each phase of DDR memory development present a number of typical challenges.

While faster speeds bring many benefits, they also introduce some issues that make design and verification more complex. The goal is to manage these issues and ensure good signal integrity. Doing so ensures system interoperability, improves device performance, and provides greater design margin. Figure 2 summarizes the DDR memory development lifecycle and lists the typical DDR verification challenges that designers and engineers need to address. Refer to the DDR Tutorial document series to learn about the techniques and tools needed to address each challenge:

– Simulation device and interconnect verification

– Probe the physical layer and perform functional tests

– Test signal integrity and troubleshoot DDR

– Find and determine the causes of data corruption and troubleshooting

– Differentiate between DRAM and controller validated read/write signals

– Ensure DDR compliance and interoperability.

Simulation device and interconnect verification

Designers have difficulty observing the characteristics of these devices when they must analyze their drivers and receivers before bringing their chips to market. This process is further complicated by the difficulty in obtaining accurate package analysis results. So how can you fully characterize and optimize your DDR memory design in a comprehensive design environment?

Probe the physical layer and perform functional tests

JEDEC defines the ball-out DDR specification for DRAM fine-pitch ball grid array (FBGA) packages. The ball-out is located on the underside of the FBGA package, which makes it difficult to probe its signals for true consistency. Engineers typically probe the signals at vias or termination resistors, but this often affects the measurement results. Issues such as signal reflections, distortion, and skew can have some adverse effects. How do you choose an appropriate method to probe to ensure that you can accurately observe the characteristics of the signal?

Test signal integrity and troubleshoot DDR

To diagnose and troubleshoot DDR device failures, engineers need to perform root cause analysis. This can prove to be a difficult and tedious task. Various design issues and system resources can cause failures, and spending too much time identifying and troubleshooting problems can delay project schedules and time to market. If you choose the right tools, you can quickly find the root cause of the failure and fix it. In addition, designers can analyze the signal until the expected bit error rate is achieved. So what tools can be used to effectively identify, diagnose and troubleshoot signal integrity issues?

Find and determine the cause of data corruption and troubleshooting

Sometimes it can be very difficult to track down rare errors or events because they don’t happen very often. What if a glitch only occurs once every 5 minutes and can only be seen in infinite persistence display mode? If we can’t track it, we don’t fully understand the conditions under which the glitch occurred. Similar scenarios also include adjacent signal transitions or ISI interference under the influence of a specific DQ pattern, which causes crosstalk and causes signal overshoot. How do you find and troubleshoot intermittent errors?

Differentiate read/write signals for DRAM and controller verification

The main DDR operations include reads and writes—both use the same strobe and data lines for signaling. To characterize the electrical and timing parameters of these signals, you need to distinguish the complex traffic on the data bus for further analysis. The traffic includes read data (output), write data (input), and high impedance states (idle). Eight data buses form a data group, and their signal sources are synchronized to a single strobe signal. To further complicate matters, the write data is 90 degrees out of phase with the read data, with the strobe signal edge as the reference, as shown in Figure 3. How can you easily and reliably distinguish between read and write cycles?

Figure 3. The strobe is active only during a data burst. Read signals are aligned to the strobe edge and write signals are centered on the strobe edge.

Ensuring DDR compliance and interoperability

The DDR specifications established by JEDEC include a series of measurements that must be performed to ensure conformance. Engineers typically perform measurements manually, record the results, and compare them to the specifications to determine if the device is compliant. These results then need to be combined into a test report for sharing or archiving. This rigorous process must be repeated for every modification or improvement to the device. How can you reduce the time and effort spent on ensuring conformance and interoperability?

Learn how to overcome these challenges in the DDR design and verification process by reading this series of DDR tutorial documents. These tutorials explain in more detail how continued advancements in DDR technology and tools can provide ever-improving solutions to your DDR memory challenges.