How to ensure compliance with DDR4 standards using an oscilloscope

Double data rate (DDR) memory technology has grown dramatically over the past five years as oscilloscope users have demanded faster, lower power, and smaller memory.

DDR4 stands for the fourth generation of SDRAM memory with double data rate. Compared with DDR3, DDR4 has a significantly increased data transfer bandwidth and surpasses previous generations in terms of speed, density and power. These technological advances have further improved the performance and energy efficiency of enterprise applications, micro server applications and tablet applications, allowing designers to design devices with smaller chips, lower power consumption and less heat dissipation.

The architecture of DDR4 memory combines key features from both DDR3 (bidirectional DQS) and a GDDR5-like data bus (CRC and data error detection capabilities). However, DDR4 signals also have some characteristics that are very different from previous generation DDR solutions. These key differences have prompted the emergence of new test methods.

Signal integrity issues

Signal integrity is critical to the reliable operation of memory systems. Testing signal integrity starts at the physical layer, where data is transmitted via the rising and falling edges of the clock. However, there are some new challenges when testing the physical layer of DDR4 memory.

Electrical, timing, and eye-diagram testing, as required by the Joint Electron Devices Engineering Council (JEDEC) standards, requires input and output measurements, which include extensive testing to ensure that the memory system is operating properly and error-free. The increased speed of DDR4 also requires measuring AC timing parameters by separating read and write cycles.

The increase in memory speed has also led to an explosion in random jitter. DDR4 is the first DRAM with super-fast speeds that must keep jitter within a specified range. Excessive jitter will reduce the data valid window, so the data valid window of DDR4 must be clearly defined.

Another concern for DDR4 device developers is interoperability. The ultimate goal is to ensure universal functionality of memory systems while improving efficiency and productivity. Only by clearly understanding the test requirements of the DDR4 specification (e.g., memory timing, eye diagram measurements, and jitter) and the test process (e.g., correct probing and simulation protocols) can you recover margins, shorten chip/system design cycles, reduce costs, and accelerate time to market. The ultimate goal is to ensure universal functionality of memory systems and achieve higher energy efficiency and productivity.

What is jitter?
Jitter is the phenomenon whereby the timing events of a signal deviate from their ideal positions.

DDR4 Testing Requirements

Timing specifications for previous generations of DDR memory were based on several risky assumptions, the biggest of which was that perfect data capture was possible as long as data setup and hold times met specifications. DDR2 and DDR3, with slower data rates and larger margins, had specifications that assumed negligible random jitter and zero bit error rate (BER). Of course, it wasn’t actually zero. For clock jitter, measuring a clock cycle for 10,000 cycles would give a BER of 1e-4, which was considered close enough to zero. The slower data transfer speeds of DDR2 and DDR3 allowed these assumptions to hold because there was enough margin before the system saw an out-of-spec result.

DDR4's faster data rates reduce margins, and random jitter can quickly close the data eye, which means increased bit error rates. If not controlled, this can create serious system reliability issues, increase design time, slow time to market, and increase design cycle costs. However, DDR4 test requirements can address these issues head-on, ensuring reliability and reducing costs.

Displaying captured waveform data as a real-time eye diagram (RTE) provides insight into jitter in serial data signals. An eye diagram is essentially an overlay of digitized bits, showing when a bit is valid (high or low). It provides a composite picture of the quality of the system's physical layer characteristics and enables peak-to-peak edge jitter and noise to be displayed in detail.

Real-time eye diagram testing performs eye height and eye width measurements to check signal integrity and estimate the data valid window. However, measuring the data eye diagram alone does not fully understand the data valid window or estimate the bit error rate. Currently, the signal integrity of the DDR4 specification measures the worst-case time margin (tDIVW) and voltage (vDIVW).

The Eye Mask test is one of the most important physical layer measurements that can be used to test overall signal integrity. From the overall jitter, the minimum time and minimum voltage margins associated with the Eye Mask can be derived. If the defined BER is large (or if there is a small amount of data), the measurement can be performed directly. If the BER being tested is small, then measuring trillions of unit intervals (UIs) will take too much time.

Eye mask testing ensures that the data eye does not exceed the mask boundaries where jitter (and bit errors) may occur. In addition, it reports the minimum margin (four timing points at the four corners of the mask) through the tDIVW measurement results (Figure 1).

Figure 1. Eye-diagram mask testing ensures that the signal does not exceed the mask boundaries, where jitter and bit errors can occur.

Eye Diagram Testing
– Data eye height and eye width can be measured
– Users can also define their own eye diagram template based on device specifications
– If the eye diagram does not meet the template, the compliance application can report a failure status

The DDR4 specification considers the key roles of jitter and BER. It is important to calculate the jitter BER measurement results, which can statistically measure the total jitter (deterministic jitter + random jitter) to understand the design's data valid window results and the probability of possible errors.

In addition to specification testing, it is also critical to adopt the correct test process and method. For example, the correct placement of the oscilloscope probe affects the consistency test results and the accurate characterization and testing of the design margin. For the JEDEC specification, the best probing point is on the ball of the DRAM package (not on the transmission line or channel, nor on the memory controller).

Simulation is another important but often overlooked step in the test process. With the increase in bus speeds and the need to obtain as much margin as possible, the simulation process can greatly help reduce design cycle time and costs.

For example, simulation helps ensure that the system can tolerate the loading effects of an interposer. This step evaluates the measured bandwidth/frequency response to ensure that the interposer does not disconnect the bus.

Finally, Keysight works closely with the JEDEC organization to ensure that its test and measurement solutions are highly consistent with the test and measurement specifications of the JEDEC standard.

Figure 2. The simulated design with appropriate loading effects is then compared to the actual scan results of the prototype to confirm that the system is functioning properly.

Technical Insight: Calculating Total Jitter
Deterministic jitter (DJ) is usually bounded and predictable and can be associated with the data stream, such as inter-symbol interference and duty cycle distortion. Random jitter (RJ) is Gaussian distributed and unbounded. As with any Gaussian distribution, as the total amount increases, the peak-to-peak value of the distribution also increases. Therefore, the total jitter (TJ) is equal to the deterministic jitter DJ plus the random jitter RJ times the BER. Understanding the composition and sources of jitter can help designers reduce the incidence of jitter in their designs, ensuring better data performance.

Solution for physical layer DDR4 testing

Three steps to accurately perform the test:

1. Choose the right probe and place it in the right location

2. Select an oscilloscope that performs the appropriate application analysis

3. Use automated compliance test applications compliant with JEDEC standards

1. Choose the right probe and place it in the right location

For computer system designs using DDR4 memory, there are several probing methods to access the memory system for testing. The first probing method applies to scenarios where the computer system has memory sockets/connectors that can be populated with DIMMs or SODIMMs. For this type of configuration, the simplest way to access the signals is to use a socket interposer (Figure 3).

Figure 3. SODIMM slot interposer

The slot interposer routes all command signals to a cable that can be connected directly to the input of a mixed signal oscilloscope (MSO) in place of an MSO cable. To access the data strobe signal (DQS) and output data (DQ), the probe tip can be soldered to the slot interposer and connected to the analog channels (Figure 4). This allows viewing of the 16 digital channels of the SODIMM as well as the DQS and DQ signals transmitted through the analog channels.

Figure 4. Using a solder-in probe head provides access to the DQS and DQ signals routed to the oscilloscope's analog channels. In this example, the probe head used is the E2677A.

Another option is DDR4 BGA probing, which is suitable for testing embedded systems (or DIMM configurations). For DDR4, the BGA interposer is designed to provide access to all signals to allow for maximum flexibility in characterizing all signals (data, address, control, command, strobe, and clock). When using this probing method, the BGA interposer is soldered between the DRAM and the board. The solder joints for connecting the oscilloscope are located on the top of the BGA (Figure 5).

Figure 5. Keysight DDR BGA interposer. Accessing signals through the oscilloscope pads around the interposer.

If space is extremely tight (particularly in a DIMM configuration), an interposer may be needed to raise the interposer off the board so that it does not interfere with any adjacent components (Figure 6). In this case, the interposer would be soldered to the bottom of the interposer.