Analysis of DDR1&2&3 Signal Integrity Test and Analysis Technology

DDR 1&2&3 Bus Overview

The full name of DDR is Double Data Rate SDRAM, or DDR for short. Now DDR technology has developed to DDR 3, which can theoretically support a speed of 1600MT/s. The DDR bus has many traces, high speed, complex operation, and difficult detection, which brings huge challenges to testing and analysis.

DDR essentially doubles the speed of SDRAM without increasing the clock frequency. It allows data to be read on both the rising and falling edges of the clock, making it twice as fast as standard SDRAM. The address and control signals are the same as traditional SDRAM, and data judgment is still performed on the rising edge of the clock.

Currently, many computers use DDR2 memory with a clock frequency of 533MHz. More advanced DDR2 memory is becoming increasingly popular, with a clock frequency between 400MHz and 800MHz. The new DDR3 memory can operate at a clock frequency between 800MHz and 1600MHz. DDR3 memory chips have another advantage: lower power consumption. Its operating voltage is 1.5 volts, lower than the 1.8 volts of DDR2 memory chips and the 2.5 volts of DDR1 memory chips. In battery-powered devices, it can extend battery life because low power consumption generates less heat, which requires less cooling.

The meanings of several new features of DDR 2&3 are: ODT (On Die Termination), DDR1 matching is placed on the motherboard, DDR2&3 matching is designed directly into the DRAM chip to improve signal quality. OCD (Off Chip Driver) is to strengthen the control function of pull-up and pull-down driving, and increase the timing margin of the signal by reducing the DQS and /DQS (DQS is the data strobe, source synchronous clock, data 1 and 0 are judged by DQS as the clock) Skew. Posted CAS is a method to improve bus utilization. AL (Additive Latency) technology is relative to the external CAS, the internal CAS performs a certain delay.

Figure 1: DDR bus architecture

Figure 1 is the architecture of the DDR bus. DQS is a source synchronous clock. DQS is used at the receiving end to read out the corresponding data DQ. Both the rising and falling edges are valid. In the DDR1 bus, DQS is a single-ended signal, while in DDR2&3, DQS is a differential signal. Both DQS and DQ are three-state signals, which are transmitted bidirectionally on the PCB trace. During the read operation, the edge of the DQS signal is aligned with the edge of the DQ signal in timing, and during the write operation, the edge of the DQS signal is aligned with the center of the DQ signal in timing. Refer to Figure 2. This brings a huge challenge to test verification: it is very difficult to separate the "read" signal from the "write" signal!

Figure 2: DDR bus "read" and "write" operation timing

In Figure 2, Addr/Cmd Bus means address/command bus, which is valid on the rising edge of the clock. The command is determined by: /CS (chip select), /RAS, /CAS, /WE (write enable), for example: "read" command is: LHLH, "write" command is: LHLL, etc. There are many operation commands, mainly NOP (no operation), Active (activation), Write, Read, Precharge (Bank closed), Auto Refresh or Self Refresh (auto refresh or self refresh), etc. (For details, please refer to: Jedec specification JESD79). Data Bus is the data bus, and the rising and falling edges of DQS determine the 0 and 1 of data DQ.

The DDR bus has many PCB traces, high speed, complex timing and operation commands, and is prone to failure. For this reason, we often use an oscilloscope to test and analyze the signal integrity of the DDR bus. The usual test content includes: signal integrity test and analysis of the clock bus; signal integrity test and analysis of the address and command bus; and signal integrity test and analysis of the data bus. The following discusses the signal integrity test and analysis technology of the DDR bus from these three aspects.

Signal integrity test analysis of DDR 1&2&3 clock buses

The test of DDR bus reference clock or clock bus is becoming more and more complicated. The main test contents can be divided into two aspects: waveform parameters and jitter. The waveform parameters mainly include overshoot, undershoot, slew rate or rise time and fall time, high and low time and duty cycle, etc. The test is relatively simple and will not be described here. The jitter test is becoming more and more complicated. In the past, it was generally only the cycle-cycle jitter that was tested. However, when the rate exceeds 533MT/s for DDR2&3, the test contents are quite a lot and cannot be ignored. Table 1 below is the specification parameters of DDR2 667. The test of these jitter parameters needs to be implemented with dedicated software, such as Agilent's N5413A DDR2 clock characterization tool. It is recommended to use a differential probe and oscilloscope with a system bandwidth of more than 4GHz for the test. The test point is close to the DRAM chip on the DIMM. It is recommended to run bus stress software such as MemoryTest on the system under test.

Table 1: DDR 2 667 clock jitter test parameters (refer to Jedec specification)

tCK(avg) is the average period of multiple continuous clocks. In order to reduce the impact of the spread spectrum clock SSC, it is required to use 200 consecutive periods to calculate tCK(avg). The calculation formula is as follows:

tJIT(per) is defined as the maximum deviation of a single cycle tCK from the average cycle tCK(avg).

tJIT(per) = min/max {tCKi-tCK(avg) where i=1 to 200 }

tJIT(cc) is defined as the difference between two consecutive clock cycles.

tJIT(cc) = min/max |tCKi+1 – tCKi|

tERR(nper) is defined as the accumulated error over multiple consecutive cycles relative to tCK(avg).

For example: n=2 is tERR(2per), n=3 is tERR(3per), n=4 is tERR(4per), etc.

tCH(avg) is defined as the average value of the pulse height width, and is also calculated for 200 consecutive pulses.

tCL(avg) is defined as the average value of the pulse low width, and is also calculated for 200 consecutive pulses.

Figure 3 is an example of test results using the N5413A, from which the worst-case test parameters can be analyzed.

Figure 3: DDR2 667 clock jitter test results using N5413A

DDR 1&2&3 address and command bus signal integrity test analysis

   The signal integrity test of DDR address and command bus mainly tests its waveform and timing parameters. The signal quality that needs to be tested for address bus An, command bus /RAS, /CAS, /WE, /CS mainly includes: Vmax (maximum voltage value), Vmin (minimum voltage value), maximum value of duration of overshoot and undershoot, slew rate, ringback, etc.; it is also necessary to test the setup time and hold time relative to the clock edge. The definition of setup time and hold time is shown in Figure 4, where tIS is the setup time and tIH is the hold time. For DDR 400, tIS and tIH are 0.7ns.

Figure 4: Definition of setup and hold times for DDR commands, addresses, and address bus

When testing the setup and hold time relative to the clock edge, it is necessary to pay attention to the position of the reference level and the capture of the worst-case waveform. As shown in Figure 5, the test of the /CS setup and hold time did not test the worst-case setup and hold time values. Therefore, we need to use the eye diagram accumulation method to find the worst-case setup and hold time.

Figure 5: Setup and hold time test of /CS signal

DDR 1&2&3 data bus signal integrity test analysis

The waveform parameter test of DQS (source synchronous clock) and DQ (data) is similar to the command address bus test, which is relatively simple and will not be introduced in detail here. For DDR1, DQS is a single-ended signal and can be tested with a single-ended probe. DDR2&3 DQS is a differential signal. It is recommended to use a differential probe to reduce the difficulty of detection. The DQS and DQ waveforms include tri-state characteristics, and the relative timing characteristics of DQS and DQ for read data (Read Burst) and write data (Write Burst). When we tested, it was not enough to just capture such a waveform and then test the setup time and hold time parameters during the "read" and "write" operations, because the data pattern is changing and the burst length is also changing. It is difficult to cover various situations by only testing a few timing parameters, and it is even more difficult to test the worst situation. Many engineers spent a week testing DDR and still could not find the key point of the problem. Therefore, we should use eye diagrams to test the "read" and "write" timing of DDR to ensure that the overall timing situation is reflected and the waveform in the worst case is captured. It is best to apply the analysis method of serial data and call templates to help make judgments.

    Based on the different phase characteristics of DDR "read" and "write" signals, I designed a software to test and analyze the "read" and "write" eye diagrams. The software uses VEE Pro 7.5 to design the interface and VEE Pro's built-in Matlab script to analyze the data. Based on the standardized AC parameter design template, it helps engineers perform the most complex part of DDR signal integrity test analysis, namely the "read" and "write" data eye diagram test and analysis.

Figure 6 is an example of the software interface and analysis results. The two figures above are user interfaces. The one on the left is the offline analysis software, which uses an oscilloscope to simultaneously collect DQS and DQ signals and saves them as *.CSV files. During the acquisition, the sampling rate is set to 20GSa/s and the storage depth is set to more than 200k to ensure that enough data is captured. At the same time, the system under test runs large software or MemoryTest tools (this memory test software can perform stress tests on the memory bus, generally used by system designers or memory designers) to allow enough data on the bus to increase the possibility of capturing various code types and the worst case. The offline software calls the collected waveform, automatically removes the three-state data, puts the "read" data together, puts the "write" data together, and based on the effective edge of DQS (removes the rising and falling edges after pre-adjustment and post-adjustment), accumulates them together to form an eye diagram, and calls the template to determine the quality of the signal and whether it meets the specification requirements.