Design of Metal Magnetic Memory Detector Based on DSP and CPLD

　　Metal magnetic memory detection technology has always had good application prospects since it was proposed, but the lack of theoretical research is the biggest bottleneck restricting the application and development of this technology. Existing theoretical research believes that the hidden defects on the surface of the ferromagnetic material structure will produce a zero-crossing point of the normal magnetic field component, making the tangential magnetic field component take the maximum value. Based on this, some detectors on the market use the zero-crossing point of the normal magnetic field component to judge the stress concentration area of ​​ferromagnetic materials. Nowadays, some scholars at home and abroad have done more research on this basis. Some scholars have obtained the magnetic field gradient by measuring the magnetic field signal, and judged the degree of magnetic memory damage according to the magnetic field gradient; other scholars have analyzed and processed the collected magnetic field signals through wavelet transform, suppressing detail coefficients, wavelet exponential descent denoising and other methods, and using multiple characteristic quantities to make qualitative and quantitative comprehensive judgments on stress concentration to improve the recognition rate of fatigue damage of ferromagnetic metal components.

　　In summary, these methods are all based on the measurement of the magnetic leakage signal of ferromagnetic materials. The metal magnetic memory detector designed in this paper is an embedded device detection system with DSP and CPLD as the core. Since the DSP chip has a fast processing speed, it can process real-time collected data at high speed, but the DSP chip resources and interfaces are limited, and the coordination with peripherals often faces requirements such as interface multiplexing and timing coordination. In order to reduce the time overhead caused by DSP controlling and communicating with off-chip modules and efficiently exert the data processing capabilities of DSP, this paper implements a peripheral control hub based on CPLD to assist the DSP chip in completing the logic control and timing coordination of peripherals, ensuring the data processing speed of the DSP chip.
 

　　1 Hardware interface design

　　The DSP used in the system is TI's TMS320F28335 processor, the CPLD used is ALTERA's EPM570, the sensor used is HONEYWELL's HMC1052 magnetoresistive sensor, and the LCD screen used is the HW480272F-0L-0A TFT LCD screen produced by Shenzhen Xushengda Electronics Factory.

　　The overall implementation process of the system is as follows: the sensor collects the magnetic memory signal on the surface of the ferromagnetic parts. The DSP quickly collects the sensor signal, processes it at high speed, and extracts the characteristic signal through the internal AD converter. The DSP transmits the signal to the CPLD through the bus. The CPLD stores the waveform display signal in the display memory SRAM, and then displays a frame of waveform data of the TFT display screen stored in the SRAM on the TFT screen. Therefore, once the waveform on the screen passes through zero, it can be judged that there is stress concentration here. In order to facilitate the human-computer communication of the system, buttons and buzzers are added to the system. The buttons are responsible for setting the relevant parameters of the system. When the stress concentration area is detected, the buzzer is responsible for the alarm. Figure 1 is the hardware structure diagram of the detector.

　　1.1 HMC1052 magnetoresistive sensor

　　The magnetoresistive sensor HMC1052 is a dual-axis linear magnetic sensor. Each sensor has a Wheatstone bridge composed of a magnetoresistive thin film alloy. When the power supply voltage is added, the sensor converts the magnetic field strength into a voltage output, and the signal voltage can be amplified to the AD sampling voltage range through an instrument amplifier. The magnetic field measurement range of HMC1052 is ±6gauss, and the sensitivity is 1.0mV/V/gauss. When the bridge is powered by 5V voltage, the full-scale output voltage range of the sensor is ±30mV. The internal AD range of the DSP is 0-3V, so the instrument amplifier reference voltage is set to 1.5V and the amplification factor is set to 50 times to achieve the AD full scale. Using the magnetic principle, the sensor HMC1052 measures the normal component Hp (y) of the scattered magnetic field on the surface of the workpiece along the coordinate XY component. Through calculation and error correction, the Hp (y) value can be obtained by the formula: Hp=√X2+Y2. The sign of Hp (y) is the same as the sign of the measurement reference direction Y. Figure 2 shows the single-axis conditioning circuit of the HMC1052 sensor. The other-axis conditioning circuit is similar to Figure 2.

　　During the manufacturing process of magnetoresistive sensor, the axis along the length of the film is selected. When the glass film alloy film is disturbed by a strong magnetic field (greater than 20 gauss), the magnetization polarity of the film will be destroyed. It is necessary to apply a transient strong magnetic field to the sensor to restore or maintain the sensor characteristics. This process only requires the DSP to provide a set or reset pulse CLOCK signal. Figure 3 is a single clock reset circuit, where CLOCK is connected to a GPIO port of the DSP, S/R- is connected to the 8th pin of HMC1052, and the sixth pin of the corresponding HMC1052 is grounded.

　　1.2 Communication between DSP, CPLD and related peripherals

　　As the working clock of DSP chip is getting higher and higher, the execution cycle of instructions is getting shorter and shorter. The peripherals connected to the system, such as buttons, display screens, buzzers, etc., have different speeds and are slower than DSP. If DSP directly controls these off-chip modules, it will bring a lot of time overhead. In this system, DSP often needs to use a variety of gate circuits, decoding circuits, timing circuits, etc. to control peripherals. In order to save the area of ​​PCB board and increase the flexibility and reliability of system design, CPLD is used to realize the peripheral circuit control of DSP, which can fully utilize the resources in CPLD, reduce the complexity of software programming, and improve the execution speed of DSP. In this way, DSP assigns an address to each peripheral, and CPLD controls the corresponding peripheral through the address line, control line and data line transmitted by DSP. For key-type peripherals, when the key is pressed, CPLD first debounces the key. After CPLD obtains the key value, it notifies DSP through interruption, and DSP reads the key value through the bus.

　　TMS320F28335 is connected to CPLD through four-bit address bus (XA［11:8］), data bus (XD［11:0］), external read/write enable signal (RD, WR), chip select signal (CS) and I/O interrupt signal. These signal lines complete the DSP's read/write operation on the relevant registers or I/O in CPLD. All peripheral DSPs attached to CPLD can be assigned a corresponding address through address line XA［8:11］. When the write instruction is executed in DSP: *(0x0400)=0x001, address bus XA［11:8］=0100B, data line XD［11:0］=0x001, and CS and WR in the control line are low level, RD is high level. After receiving the bus level, CPLD performs operations such as address latching and data decoding, and can control the peripherals assigned to the corresponding address. The connection relationship between CPLD and DSP is shown in Figure 4.

　　1.3 TFT true color LCD screen

　　The resolution of the LCD screen is 272×480 and the size is 4.3 inches. The display color is 16 bits, RGB occupies 6 bits, 5 bits, and 6 bits respectively, and it uses a 3.3V voltage for power supply. A 16×256kB SRAM is attached to the CPLD as the display memory of the display screen to store a frame of screen display data. The CPLD stores the data uploaded from the DSP bus into the display memory first, and then reads it out from the display memory, and displays the waveform on the LCD screen in conjunction with the LCD screen drive timing. Figure 5 is the LCD control diagram.

　　

　　2 Software Design

　　The main functions realized by this instrument are: magnetic flux leakage signal acquisition and processing, signal waveform LCD display, sound alarm and key function setting. Among them, signal acquisition is completed by the internal AD interrupt of DSP, and only the relevant registers need to be set. Since the waveform display and sound alarm are directly sent by DSP to CPLD through the bus; and the key function setting is: when the key is pressed, CPLD notifies DSP through interruption, and then DSP reads the key value through the bus. According to these functions, the system software flow charts as shown in Figures 6 and 7 are drawn, which respectively represent the internal program flow of the two CPUs. Figure 6 is the signal waveform display and sound alarm software design flow chart, and Figure 7 is the key function setting flow chart.

　　3 Conclusion

　　As a new non-destructive testing technology, metal magnetic memory has been increasingly widely used in the fields of petrochemical pipelines, power station turbines, engineering machinery and equipment. The detector designed with a combination of DSP and CPLD can not only ensure high-speed signal acquisition and processing, but also utilize the hardware resources inside the CPLD, greatly simplifying the time overhead of DSP accessing peripherals and improving the execution speed of the entire system. At the same time, CPLD reserves certain expansion interfaces to facilitate future system updates and upgrades.