Software and Hardware Design of Graphic Display System of Digital Oscilloscope Based on FPGA

　　When using FPGA to design functional circuits, people can shift their thinking from the traditional system integration type with single-chip microcomputer or DSP chip as the core to a single dedicated chip type design. Although the traditional oscilloscope is fully functional, its application is limited by a series of problems such as large size, heavy weight, high cost, etc. In view of this, portable digital storage collectors came into being. It uses new technologies such as LCD display, high-speed A/D acquisition and conversion, ASIC chip, etc. It has strong practicality and huge market potential. It also represents a development trend of contemporary electronic measuring instruments, that is, the development towards handheld instruments with multiple functions, small size, light weight and easy use.

　　1 System overall design reading and writing

　　According to the design requirements: display more than 2 characters or patterns on the oscilloscope, such as displaying 0-9 ten numbers and English characters, images, etc., combined with the oscilloscope display principle, the circuit is designed as shown in Figure 1. The numbers or symbols to be displayed are modulo to obtain their binary form. The converted data is sent to the FPGA internal RAM for storage.

　　

　　In the design, we use XILINX's SPARTAN-3 chip as the controller to complete the control of the total numerical control part, keyboard and display interface part. Adopt eight-bit (or higher bit) D/A conversion to convert the binary digital quantity output by the FPGA chip to analog, and get its voltage after passing through the high-speed operational amplifier. It is divided into two channels, X and Y, and output to the oscilloscope. According to the principle of oscilloscope, the numbers (or graphics) are displayed on the screen. The Z channel is another independent channel to control the brightness of the displayed digital.

　　2 System Hardware Design

　　2.1 Overall control module

　　Based on this design, the part of the system control module is a logic device with a mask programmable gate array - FPGA.

　　Spartan series FPGA is a representative of the high cost-effective products among Xilinx's programmable logic products, and Spartan-Ⅲ series FPGA is designed for users who need large capacity and low price electronic applications. This system uses the XC3S200 chip of XILINX, and its technical parameters are as follows:

　　●4 320 logic units;

　　●System gate density 200 k;

　　●CLB array 24*20, 480 in total;

　　●Maximum user I/O 173, maximum differential I/O 76;

　　●Distributed RAM capacity 30 Kbit, Block RAM capacity 216Kbit;

　　●Embedded 18x18 multiplier supports high-performance DSP applications;

　　●PCI and high-speed differential signaling with LVDS.

　　2.2 Storage unit module

　　Since FPGA is based on CMOS SRAM technology, it does not have power-off protection function. When there is no power supply, the configured data is lost and the chip function is also lost. Therefore, this design adopts the FLASH memory online reconfiguration method. [page]

　　 

 

 

　　2.3 Peripheral circuit module

　　2.3.1 D/A Conversion

　　In the selection of D/A, we use the DAC0832 of American Semiconductor Company, which has the characteristics of 8-bit parallel, medium speed (setup time 1 us), current type, low price, etc. It has two working modes: single buffer working mode and double buffer working mode. In single buffer working mode, one register works in direct state and the other works in controlled latch state. When multi-phase D/A is not required to output simultaneously, single buffer mode can be used. At this time, only one write operation is required to start conversion, which can improve the data throughput of D/A. In double buffer working mode, both registers work in controlled latch state. When multiple analog quantities are required to output simultaneously, double buffer mode can be used.

　　Its technical parameters are: setup time 1 us; 8-bit parallel; low power consumption 20 mW; support voltage: 5 V ~ 15 V. [page]

　　2.3.2 Operational Amplification

　　After D/A conversion, we get a current signal, and what needs to be input into the oscilloscope is a voltage signal, so an operational amplifier is used for conversion, and the operational amplifier is designed to be adjustable. By adjusting it, the output voltage can be adjusted to achieve the purpose of controlling the display amplitude. This design uses the LM741 series operational amplifier, and its technical indicators are as follows:

　　

 

　　3 System Software Design

　　Based on the functions and flexibility of VHDL language, its advantages of non-dependency and portability, this design is implemented in FPGA programming using VHDL language. Overall design idea: Use 50 MHz external clock control to control the frequency division inside the FPGA, and obtain the clock signal required for the design under the action of the frequency division module. Select the module part to be displayed inside the ROM by key selection, scan in the X and Y directions to obtain preliminary data, and add a Z direction scan to control the brightness of the displayed graphics. By storing all "1"s in a ROM as a cache, the purpose of eliminating zero points is achieved. Transfer the data in the ROM to the RAM, perform mode conversion through ping-pong exchange operations, and finally input the oscilloscope through the peripheral circuit to achieve display. Overall flow chart:

　　

 

　　4 Conclusion

　　This article is the hardware/software design ideas and design solutions of the digital oscilloscope graphic display system based on FPGA. After the design of this system is completed, the test shows that the system can display the corresponding graphics and text, and the displayed graphics and text are basically consistent with the expectations. The design meets the needs of the system, and more importantly, it has strong flexibility and controllability, while making the display faster and faster, and has a very broad application prospect.