An FPGA Design and Application of Taxi Meter

O Introduction

FPGA (Field Programmable Gate Array) is a high-density programmable logic device that supports system programming and can implement different logic functions by writing different configuration data. Using FPGA to design electronic systems has obvious characteristics such as short design cycle and easy modification. It is particularly suitable for scientific experiments, prototype development and small-batch production of electronic products.

In this paper, a taxi meter is designed based on FPGA devices using EDA tool software Max+P1usⅡ. It can intuitively display the mileage of the taxi and the fees payable by the passengers in the form of decimal numbers, and has certain practical application value.

1 System Design Requirements

The taximeter to be designed is required to display the mileage and the fare to be paid by the passenger, with the mileage accurate to 0.1 km and the fare to be paid by the passenger accurate to 0.1 yuan, and the display must be in decimal form. The taxi fare standard is: the starting fare is 6 yuan, and the mileage is the starting fare within 3 km; when the mileage is between 3 and 7 km, 1.6 yuan will be added for every kilometer traveled; when the mileage exceeds 7 km, 2.4 yuan will be added for every kilometer traveled.

2 System Design

The system can be designed with discrete components or with a single-chip microcomputer. The use of programmable FPGA has obvious characteristics such as short design cycle and easy modification. With the rapid development of programmable logic devices and EDA software, more and more electronic systems are designed with FPGA. Once the system reaches a certain scale of mass production, it is also easier to convert it into ASIC chip design. Therefore, a taxi meter is designed based on FPGA. In the EDA tool software MAX+plusⅡ, this system uses a combination of hardware description language Verilog HDL and schematic design to design each module, and finally composes each module into the entire system.

Taxis can display the mileage they have traveled by generating pulses through the rotation of the wheels, and then counting the pulses through a counter. Assume that a taxi generates a pulse every 2 meters it travels. Since the mileage must be accurate to 0.1 km, that is, 100 meters, a new pulse signal must be output every 50 pulses, which is called the 100-meter pulse signal. As the clock signal of the mileage counter, it can be obtained by dividing the frequency with a counter with a modulus of 50.

The mileage counter can be realized with a three-digit BCD code counter, which can display up to 999. The first two digits are integers, and the third digit is a decimal, which means that the maximum mileage that can be displayed is 99.9 km. Since taxis are mostly in urban areas and suburbs, the three-digit BCD code counter can realize mileage counting. The mileage counter will also periodically output a pulse signal every time it counts 1 km, which is called a 1 km pulse signal, which can be realized through a certain combination circuit.

The core part of the system is how to implement the charging. Here we need to design a BCD code adder. Based on the starting price, according to the different mileage and the charging standard, a unit price is added for each additional km. The unit price can be generated by programming in Verilog HDL. The overall design block diagram of the system is shown in Figure 1.

2.1 Unit price generation module

The Verilog HDL source program of the unit price generation module is as follows:

The input signals bai and shi are the two-digit integer mileage output by the mileage counter, and the output signal jia is the unit price generated according to the charging standard, which is output in the form of a three-digit BCD code, with the first two digits being integers and the third digit being a decimal. That is, when the mileage is within 3 km, jia=0; when the mileage is between 3 and 7 km, jia=016 (1.6 yuan); when the mileage exceeds 7 km, jia=024 (2.4 yuan).

The advantage of using Verilog HDL to write programs to implement module functions is that when the taxi fare standards change, the new design can be easily completed by rewriting the program, which is much more convenient than modifying the hardware circuit. This is also an important advantage of using Verilog HDL to implement module functions. [page]

2.2 Three-digit BCD code adder

The system uses a three-digit BCD adder, which can perform three-digit decimal addition operations. The output of the adder is the fare that the passenger has to pay. Here, the first two digits are integers, and the third digit is a decimal, which means that the maximum that can be displayed is 99.9 yuan. The three-digit BCD adder is composed of three one-digit BCD adders cascaded together.

A single-bit BCD code consists of four binary digits. The addition of four binary digits will produce a number greater than 9, and appropriate adjustments must be made to produce the correct result. The Verilog HDL source code of a single-bit BCD code adder is as follows:

The simulation waveform and generated module symbol of a one-bit BCD code adder module are shown in Figures 2 and 3.

In this module, A and B are the input BCD codes, CIN is the carry signal from the low bit, CO is the carry output signal generated by this chip to the high bit, and SUM is the sum of two numbers. The three-digit BCD code adder is composed of three cascaded modules. Its circuit schematic and simulation waveform are shown in Figures 4 and 5.

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2.3 Buffer module

The output of the three-digit BCD code adder passes through the buffer and is fed back to the input end as an addend. Under the action of the 1km pulse signal, each pulse is added to the unit price to form a continuous accumulation function. The buffer also has a control input terminal LD. When LD=0, under the action of the 1km pulse, the output starting price is 6 yuan; when LD=1, under the action of the 1km pulse, the output is equal to the input. The Verilog HDL source program of the buffer is as follows:

2.4 Overall Circuit

Connecting each module into an overall circuit according to the input-output relationship is shown in Figure 6.

In the overall circuit, clk is the original clock input terminal, cr is the asynchronous reset terminal, q[11. ． O] outputs the mileage, and jiaqian[11. ． O] outputs the fare that the passenger should pay.

3 System Simulation Verification

The simulation waveform of the overall circuit is shown in Figure 7.

It can be seen from the system simulation waveform 7(a) that when the reset terminal cr=0, the mileage is immediately reset, and the fare to be paid by the passenger is displayed as a three-digit decimal number 060 (starting price 6 yuan), indicating that the passenger has just boarded the car. When the reset terminal cr=1, the taxi starts to move, and the mileage and fare are counted. The mileage is displayed as a three-digit decimal number, with the first two digits being integers and the third digit being a decimal, that is, it is counted once every 100 meters.

It can be seen from the system simulation waveform 7(b) that when the vehicle travels 3 km, the cost increases from 6 yuan to 7.6 yuan, and when the vehicle travels 4 km, the cost increases from 7.6 yuan to 9.2 yuan. When the vehicle travels between 3 and 7 km, the cost increases by 1.6 yuan for every kilometer traveled.

The system simulation waveform in Figure 7(c) shows the gradual accumulation of costs after every 1 km of driving. The system simulation waveform fully verifies the expected design requirements.

4 Conclusion

The simulation verification shows that the taxi meter designed in this paper can normally display the mileage and the fees to be paid by passengers, which meets the predetermined charging standards and functional requirements. The design based on FPGA has high integration and short design cycle. Especially when the charging standards change, it is easy to complete the new design by rewriting the Verilog HDL source program.