Design and verification of DDR read and write control using FPGA IP

Publisher:莫愁前路Latest update time:2007-03-02 Source: 电子产品世界Keywords:embedded  image  clock Reading articles on mobile phones Scan QR code
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Introduction

With the continuous development of high-speed processors, the application fields of embedded systems are becoming more and more extensive, the scale of digital signal processing is also getting larger and larger, and the size of RAM in the system is increasing, such as video surveillance, image data acquisition and other fields, image The real-time processing requirements for RAM bandwidth are increasing. The bandwidth of traditional SDRAM has gradually been unable to meet application requirements. DDR SDRAM (double rate SDRAM) uses the rising and falling edges of the clock CLK signal to transmit data on both edges; Compared with traditional SDRAM, which only transmits on the rising edge of the clock, the transmission bandwidth is doubled. DDR RAM has begun to be widely used in embedded systems and is gradually replacing traditional SDRAM.

The increase in the operating speed of DDR RAM places higher requirements on the design of control timing for designers; moreover, DDR memory uses the SSTL-II standard that supports 2.5V voltage, instead of the 3.3V used by SDRAM. Voltage LVTTL standard. Many processors do not have DDR RAM controllers, which makes it more difficult for designers to use DDR RAM. It is often necessary to insert a controller into the design to control the memory by a microprocessor or DSP.

Field programmable gate arrays (FPGAs) have been widely used in embedded systems. Many FPGAs now provide interface features for DDR SDRAM: their input and output pins are compatible with SSTL-II electrical characteristics, and internally provide hardware resources such as DDR flip-flops and phase-locked loops. Using these features, it is relatively easy to design high-speed DDR RAM controllers with reliable performance. In response to this problem, this article introduces a method of using Lattice FPGA and IP to implement DDR RAM control and verification.

LatticeXP

LatticeXP devices combine non-volatile FLASH cells and SRAM technology to enable instant-on and infinitely reconfigurable single-chip solutions. Save user configuration files in the FLASH unit array. When powered on, the configuration file is transferred from the FLASH memory to the configuration SRAM within 1 millisecond, completing instant power on.

The device is internally divided into: PIC (programmable I/O unit), non-volatile FLASH MEMORY, SYSCONFIG configuration port, PFU (programmable function unit), PLL (analog phase-locked loop), PFF (non-RAM/ROM function Programmable logic unit), EBR (embedded RAM block), JTAG port and other parts (see Figure 1).

Figure 1 LatticeXP internal structure diagram

DDR controller IP generation

IPExpress is a tool for generating IP modules in Lattice development software. It can generate IP modules according to the parameters set by the user and is very convenient to use.

Click Start IPexpress to enter the generation interface (see Figure 2). Select the DDR SDRAM project on the left, and set the project name and file save address on the right.

Figure 2 IPexpress interface

Click Next to start entering parameter settings (see Figure 3). Here you set the row and column parameters of the DDR RAM, as well as the Bank. These parameters are set according to the DDR RAM chip manual. The DDR RAM particles used in this article are Hyundai's HY5DU561622, 16M x16, 4bank particles.

Figure 3 Parameter configuration of rows and columns of DDR RAM.

Next, set the timing delay (see Figure 4).

Figure 4 DDR RAM particle timing parameter configuration

Here set parameters such as tRAC (row access cycle, RAS Access Cycle/Delay), tCAC (column access cycle, CAS Access Cycle/Delay). These parameters are listed in detail in the manual of the DDR RAM particle chip. It should be pointed out in particular that since chip providers will give different delay parameters for different DDR standards, such as DDR400, DDR333, etc., there will be several different lists in ns. Depending on the design, refer to Different forms. Because the IP generator uses a single parameter setting and the unit is CLK, it needs to be converted and set according to the design standards and clock frequency. This article uses the DDR266 standard, the clock is 133MHz, and the corresponding clock cycle is 1/133MHz, which is about 7.5ns. In this way, the TRCD of the chip in the DDR266 standard is 20ns (minimum value), which corresponds to 3 in the IP parameters. Other parameters are similarly converted.
After the settings are completed, click generate to generate the IP code file, as shown in Figure 5.

Figure 5 IP generation

Usage and verification of DDR controller IP

The interface structure of the generated DDR Controller IP is shown in Figure 6.

Figure 6 DDR Controller interface

RAM interface corresponds to DDR RAM interface signals according to the definition of signals. The other end is the user interface, including reset, clock, address, data, read and write, status signals, etc. Data is sent through the user interface and sent to the address used by the DDR RAM through IP control timing.
The test of IP is implemented by verifying data writing and reading. The test block diagram is shown in Figure 7.

Figure 7 Test principle block diagram

Create two RAM areas inside the FPGA for data storage. Here, the RAM block inside the FPGA is used to create two RAM storage areas of 256×32b size. Write FPGA code to make a simple pseudo-random sequence generator to generate a 32-bit random data sequence through a simple XOR algorithm. The generated data is stored in one of the RAMs, and is also sent to the user interface of the IP and written into the DDR RAM.

After the 256-depth storage area is full, data is read back from the DDR RAM. And send the read data to another RAM inside the FPGA. The data at the addresses in the two RAMs are compared. If the data is consistent, it means that the DDR RAM is reading and writing normally; if it is different, it means that there is an error in the DDR RAM reading and writing operations.

Since this design uses a DIMM memory module with a capacity of 512Mb, during testing, the data address adopts the base address plus index method. After each test of 256×32b data is completed, when the cycle enters the next test, the starting base address is increased by 256, and then the data operation is performed. In this way, the 512M data address space can be scanned completely, making the test more complete. This testing method uses small blocks of addresses and operates multiple times, which can reduce the usage of internal RAM in the FPGA.

The test code written in this article is written in Verilog language, and the logic is shown in Figure 8.

Figure 8 Test code logic state machine

Hardware test results

This experiment was conducted on Lattice's XP advanced version demo board.

The FPGA used is LFXP10C-5F384, the memory module is Kingston 512M notebook memory module, and the RAM particles are modern HY5DU561622. The DDR266 was tested to run continuously for 2 hours. There was no abnormality in the data and the DDR read and write operations were completely normal.

Conclusion

DDR RAM is used more and more in embedded systems. Using FPGA in the design not only makes the design flexible, but also allows the comprehensive design of peripheral digital devices into the FPGA, which greatly improves the cost-effectiveness of the system design.

References :
1. Hu Wei, Application of DDR SDRAM in embedded systems, Microcontroller and Embedded System Applications, 2006.3
2. LatticeXP family handbook. Lattice semiconductor Co.,2006.6
3.Lattice DDR1/2 controller user guide.Lattice semiconductor Co.,2006.6

Keywords:embedded  image  clock Reference address:Design and verification of DDR read and write control using FPGA IP

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